参数资料
| 型号： | ADT7468ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/81页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADT7468 |
| 标准包装： | 1 |
| 其它名称： | EVAL-ADT7468EB EVAL-ADT7468EB-ND |
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ADT7468
6.
7.
8.
The master sends a data byte.
The slave asserts ACK on SDA.
The master asserts a stop condition on SDA to end the
transaction.
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that
allows an interrupting device to identify itself to the host when
multiple devices exist on the same bus.
This operation is illustrated in Figure 20.
The SMBALERT output can be used as either an interrupt
1
2
3
4
5
6
7 8
output or an SMBALERT. One or more outputs can be
S
SLAVE
ADDRESS
W A
SLAVE
ADDRESS
A DATA A P
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the following
Figure 20. Single Byte Write to a Register
procedure occurs:
READ OPERATIONS
The ADT7468 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single
register. The register address must have been set up previously.
In this operation, the master device receives a single byte from a
slave device as follows:
1.
2.
3.
SMBALERT is pulled low.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general call
address that must not be used as a specific device address.
The device whose SMBALERT output is low responds to
the alert response address, and the master reads its device
address. The address of the device is now known and can
be interrogated in the usual way.
1.
2.
3.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts ACK on SDA.
4.
5.
If more than one device’s SMBALERT output is low, the
one with the lowest device address has priority in accor-
dance with normal SMBus arbitration.
Once the ADT7468 has responded to the alert response
4.
5.
6.
The master receives a data byte.
The master asserts NO ACK on SDA.
The master asserts a stop condition on SDA and the
address, the master must read the status registers and the
SMBALERT is cleared only if the error condition is absent.
SMBUS TIMEOUT
transaction ends.
In the ADT7468, the receive byte protocol is used to read a
single byte of data from a register whose address has previously
been set by a send byte or write byte operation. This operation
is illustrated in Figure 21.
The ADT7468 includes an SMBus timeout feature. If there is no
SMBus activity for 35 ms, the ADT7468 assumes that the bus is
locked and releases the bus. This prevents the device from
locking or holding the SMBus expecting data. Some SMBus
controllers cannot handle the SMBus timeout feature, so it can
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5
6
be disabled.
SLAVE
S R A
ADDRESS
DATA A P
Configuration Register 1 (Reg. 0x40)
<6> TODIS = 0, SMBus timeout enabled (default).
Figure 21. Single Byte Read from a Register
<6> TODIS = 1, SMBus timeout disabled.
Rev. 3 | Page 14 of 81 | www.onsemi.com
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