参数资料
| 型号： | ADT7468ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 35/81页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADT7468 |
| 标准包装： | 1 |
| 其它名称： | EVAL-ADT7468EB EVAL-ADT7468EB-ND |
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ADT7468
MISCELLANEOUS FUNCTIONS
OPERATING FROM 3.3 V STANDBY
The ADT7468 has been specifically designed to operate from a
3.3 V STBY supply. In computers that support S3 and S5 states,
the core voltage of the processor is lowered in these states. If
using the dynamic T MIN mode, lowering the core voltage of the
processor changes the CPU temperature and changes the
dynamics of the system under dynamic T MIN control. Likewise,
when monitoring THERM, the THERM timer should be
disabled during these states.
Dynamic T MIN Control Register 1 (Reg. 0x36)
<1> VCCPLO = 1
When the power is supplied from 3.3 V STBY and the V CCP
voltage drops below the V CCP low limit, the following occurs:
VID0
VID1
VID2
VID3
VID4
TACH1
TACH2
TACH3
1.
2.
Status Bit 1 (V CCP ) in Status Register 1 is set.
SMBALERT is generated, if enabled.
TACH4
PWM2
3.
THERM monitoring is disabled. The THERM timer
PWM3
PWM1/XTO
should hold its value prior to the S3 or S5 state.
Figure 47. XNOR Tree Test
4.
5.
Dynamic T MIN control is disabled. This prevents T MIN from
being adjusted due to an S3 or S5 state.
The ADT7468 is prevented from entering the shutdown
state.
POWER-ON DEFAULT
When the ADT7468 is powered up, it polls the V CCP input.
If V CCP stays below 0.75 V (the system CPU power rail is not
powered-up), then the ADT7468 assumes the functionality of
Once the core voltage, V CCP , goes above the V CCP low limit,
everything is re-enabled and the system resumes normal
operation.
XNOR TREE TEST MODE
The ADT7468 includes an XNOR tree test mode. This mode is
useful for in-circuit test equipment at board-level testing. By
applying a stimulus to the pins included in the XNOR tree, it is
possible to detect opens or shorts on the system board.
The XNOR tree test is invoked by setting Bit 0 (XEN) of the
XNOR tree test enable register (Reg. 0x6F).
Figure 47 shows the signals that are exercised in the XNOR tree
test mode.
the default registers after the ADT7468 is addressed via any
valid SMBus transaction.
If V CCP goes high (the system processor power rail is powered
up), then a fail-safe timer begins to count down. If the
ADT7468 is not addressed by any valid SMBus transaction
before the fail-safe timeout (4.6 s) lapses, then the ADT7468
drives the fans to full speed. If the ADT7468 is addressed by a
valid SMBus transaction after this point, the fans stop, and the
ADT7468 assumes its default settings and begins normal
operation.
If V CCP goes high (the system processor power rail is powered
up), then a fail-safe timer begins to count down. If the
ADT7468 has been addressed by a valid SMBus transaction
before the fail-safe timeout (4.6 sec) lapsed, then the ADT7468
operates normally, assuming the functionality of all the default
registers. See the flow chart in Figure 48.
Rev. 3 | Page 35 of 81 | www.onsemi.com
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相关代理商/技术参数 |
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| ADT7470 | 制造商:AD 制造商全称:Analog Devices 功能描述:Temperature Sensor Hub and Fan Controller |
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