参数资料
型号: ADT7468ZEVB
厂商: ON Semiconductor
文件页数: 64/81页
文件大小: 0K
描述: BOARD EVAL FOR ADT7468
标准包装: 1
其它名称: EVAL-ADT7468EB
EVAL-ADT7468EB-ND
ADT7468
Table 19. Temperature Reading Registers (Power-On Default = 0x01) 1, 2, 3
Register Address
0x25
0x26
0x27
R/W
Read only
Read only
Read only
Description
Remote 1 temperature reading 3, 4 (8 MSBs of reading).
Local temperature reading (8 MSBs of reading).
Remote 2 temperature reading 3, 4 (8 MSBs of reading).
1
2
3
4
If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended
resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).
In twos complement mode, a temperature reading of ?128°C (0x80) indicates a diode fault (open or short) on that channel.
In Offset 64 mode, a temperature reading of ?64°C (0x00) indicates a diode fault (open or short) on that channel.
Table 20. Fan Tachometer Reading Registers (Power-On Default = 0x00) 1
Register Address
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
R/W
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Description
TACH1 low byte
TACH1 high byte
TACH2 low byte
TACH2 high byte
TACH3 low byte
TACH3 high byte
TACH4 low byte
TACH4 high byte
1
These registers count the number of 11.11 μs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).
The number of TACH pulses used to count can be changed using the fan pulses per revolution register (Reg. 0x7B). This allows the fan speed to be accurately
measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until
read. At power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts
?
?
?
?
?
from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following:
Stalled or blocked (object jamming the fan).
Failed (internal circuitry destroyed).
Not populated. (The ADT7468 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should
be set to 0xFFFF.)
Alternate function, for example, TACH4 reconfigured as THERM pin.
2-wire instead of 3-wire fan.
Table 21. Current PWM Duty Cycle Registers (Power-On Default = 0x00) 1
Register Address
0x30
0x31
0x32
R/W
Read/write
Read/write
Read/write
Description
PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
1
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7468 reports the PWM duty cycles
back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers
report back 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 22. Operating Point Registers (Power-On Default = 0x64) 1, 2, 3
Register Address
0x33
0x34
0x35
R/W 3
Read/write
Read/write
Read/write
Description
Remote 1 operating point register (default = 100°C).
Local temperature operating point register (default = 100°C).
Remote 2 operating point register (default = 100°C).
1
2
3
These registers set the target operating point for each temperature channel when the dynamic T MIN control feature is enabled.
The fans being controlled are adjusted to maintain temperature about an operating point.
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Rev. 3 | Page 64 of 81 | www.onsemi.com
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