参数资料
| 型号： | ADT7468ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 67/81页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADT7468 |
| 标准包装： | 1 |
| 其它名称： | EVAL-ADT7468EB EVAL-ADT7468EB-ND |
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ADT7468
Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x01)
Bit
<0>
Name
STRT
R/W
Read/write
Description
Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.
Logic 0 disables monitoring and PWM control based on the default power-up limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the
default settings are enabled. This bit becomes read-only and cannot be changed once Bit 1 (LOCK bit)
has been written. All limit registers should be programmed by BIOS before setting this bit to 1.
(Lockable.)
<1>
LOCK
Write once
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become
read-only and cannot be modified until the ADT7468 is powered down and powered up again. This
prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable.)
<2>
RDY
Read-only
This bit is set to 1 by the ADT7468 to indicate only that the device is fully powered-up and ready to
begin system monitoring.
<3>
<4>
FSPD
VxI
Read/write
Read/write
When set to 1, this bit runs all fans at full speed. Power-on default = 0. This bit never gets locked.
BIOS should set this bit to a 1 when the ADT7468 is configured to measure current from an ADI ADOPT?
VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display
CPU watts usage. (lockable.)
<5>
FSPDIS
Read/write
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan
spin-up timeout selected.
<6>
TODIS
Read/write
When this bit is set to 1, the SMBus timeout feature is enabled. This allows the ADT7468 to be used with
SMBus controllers that cannot handle SMBus timeouts. (lockable.)
<7>
V CC
Read/write
When this bit is set to 1, the ADT7468 rescales its V CC pin to measure 5 V supply. If this bit is 0, the
ADT7468 measures V CC as a 3.3 V supply. (lockable.)
Table 27. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)
Bit
<0>
Name
2.5 V
R/W
Read only
Description
2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<1>
V CCP
Read only
V CCP = 1 indicates that the V CCP high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<2>
V CC
Read only
V CC = 1 indicates that the V CC high or low limit has been exceeded. This bit is cleared on a read of the
status register only if the error condition has subsided.
<3>
<4>
5 V/
THERM
timer
R1T
Read only
Read only
A one indicates the 5 V high or low limit has been exceeded. This bit is cleared on a read of the status
register only if the error condition has subsided. If Pin 20 is configured as THERM, this bit is asserted when
the timer limit has been exceeded.
R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
<5>
LT
Read only
LT =1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of
the status register only if the error condition has subsided.
<6>
R2T
Read only
R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a
read of the status register only if the error condition has subsided.
<7>
OOL
Read only
OOL = 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR
of all status bits in Status Register 2. Software can test this bit in isolation to determine whether any of
the voltage, temperature, or fan speed readings represented by Status Register 2 are out-of-limit, which
saves the need to read Status Register 2 during every interrupt or polling cycle.
Rev. 3 | Page 67 of 81 | www.onsemi.com
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