参数资料
| 型号： | ADT7468ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 77/81页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADT7468 |
| 标准包装： | 1 |
| 其它名称： | EVAL-ADT7468EB EVAL-ADT7468EB-ND |
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ADT7468
Table 5 1. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)
Bit
<0>
Name
ALERT
R/W 1
Read/write
Description
ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate
out-of-limit error conditions.
ALERT = 0, Pin 10 (PWM2/SMBALERT) is configured as the PWM2 output.
<1>
THERM
Read/write
THERM Enable = 1 enables THERM functionality on Pin 20 and Pin 14, if Pin 14 is configured as
THERM, determined by Bits 0 and 1 (PIN14FUNC) of Configuration Register 4. When THERM is
asserted, if the fans are running and the boost bit is set, the fans run at full speed. Alternatively,
THERM can be programmed so that a timer is triggered to time how long THERM has been asserted.
<2>
BOOST
Read/write
When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum
programmed duty cycle for fail-safe cooling.
<3>
FAST
Read/write
FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement
rate from once per second to once every 250 ms (4 ×).
<4>
DC1
Read/write
DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by
dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<5>
DC2
Read/write
DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by
dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<6>
DC3
Read/write
DC3 = 1, enables TACH measurements to be continuously made on TACH3. Setting this bit prevents
pulse stretching, because it is not required for dc-driven motors.
<7>
DC4
Read/write
DC4 = 1, enables TACH measurements to be continuously made on TACH4. Setting this bit prevents
pulse stretching, because it is not required for dc-driven motors.
1
This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 5 2. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00)
Bit
<7:1>
Name
TMR
R/W
Read only
Description
Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time
exceeds 45.52 ms.
<0>
ASRT/
TMR0
Read only
This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM
assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This
allows THERM assertion times from 45.52 ms to 5.82 secs to be reported back with a resolution of
22.76 ms.
Table 5 3. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00)
Bit
<7:0>
Name
LIMT
R/W
Read/write
Description
Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit
limit with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 secs to be
programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register
2 (Reg. 0x42) is set. If the limit value is 0x00, then an interrupt is generated immediately on the
assertion of the THERM input.
Rev. 3 | Page 77 of 81 | www.onsemi.com
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