参数资料
型号: ADT7468ZEVB
厂商: ON Semiconductor
文件页数: 69/81页
文件大小: 0K
描述: BOARD EVAL FOR ADT7468
标准包装: 1
其它名称: EVAL-ADT7468EB
EVAL-ADT7468EB-ND
ADT7468
Table 31. Temperature Limit Registers 1
Register Address
0x4E
0x4F
0x50
0x51
0x52
0x53
R/W
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Description 2
Remote 1 temperature low limit
Remote 1 temperature high limit
Local temperature low limit
Local temperature high limit
Remote 2 temperature low limit
Remote 2 temperature high limit
Power-On Default
0x81
0x7F
0x81
0x7F
0x81
0x7F
1
2
Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock
bit has no effect on these registers.
High Limits: An interrupt is generated when a value exceeds its high limit (> comparison). Low Limits: An interrupt is generated when a value is equal to or below its
low limit ( ≤ comparison).
Table 32. Fan Tachometer Limit Registers 1
Register Address
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
R/W
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Read/write
Description
TACH1 minimum low byte
TACH1 minimum high byte/Single channel ADC
channel select
TACH2 minimum low byte
TACH2 minimum high byte
TACH3 minimum low byte
TACH3 minimum high byte
TACH4 minimum low byte
TACH4 minimum high byte
Power-On Default
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
1
Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2
to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.
Table 3 3. Register 0x55—TAC H 1 Minimum High Byte (Power-On Default = 0xFF)
Bits
<4:0>
Name
Reserved
R/W
Read only
Description
These bits are reserved when Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode).
Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte.
<7:5>
SCADC
Read/write
When Bit 6 of Config 2 Register (0x73) is set (single channel ADC mode), these bits are used to select the
only channel from which the ADC makes measurements. Otherwise, these bits represent Bits <7:5> of
the TACH1 minimum high byte.
Rev. 3 | Page 69 of 81 | www.onsemi.com
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