参数资料
| 型号： | ADT7468ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 70/81页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADT7468 |
| 标准包装： | 1 |
| 其它名称： | EVAL-ADT7468EB EVAL-ADT7468EB-ND |
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ADT7468
Table 34. PWM Configuratio n Registers
Register Address
0x5C
0x5D
0x5E
R/W 1
Read/write
Read/write
Read/write
Description
PWM1 configuration.
PWM2 configuration.
PWM3 configuration.
Power-On Default
0x82
0x82
0x82
Bit
<2:0>
Name
SPIN
R/W
Read/write
Description
These bits control the startup timeout for PWMx. The PWM output stays high until
two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal
during the fan TACH measurement directly after the fan startup timeout period, then
the TACH measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If
the TACH minimum high and low bytes contain 0xFFFF or 0x0000, then the Status
Register 2 bit is not set, even if the fan has not started.
000 = No startup timeout
001 = 100 ms
010 = 250 ms (default)
011 = 400 ms
100 = 667 ms
101 = 1 sec
110 = 2 secs
111 = 4 secs
<3>
<4>
SLOW
INV
Read/write
Read/write
SLOW = 1 makes the ramp rates for acoustic enhancement four times longer.
This bit inverts the PWM output. The default is 0, which corresponds to a logic high
output for 100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100%
duty cycle corresponds to a logic low output.
<7:5>
BHVR
Read/write
These bits assign each fan to a particular temperature sensor for localized cooling.
000 = Remote 1 temperature controls PWMx (automatic fan control mode).
001 = local temperature controls PWMx (automatic fan control mode).
010 = Remote 2 temperature controls PWMx (automatic fan control mode).
011 = PWMx runs full speed.
100 = PWMx disabled (default).
101 = fastest speed calculated by local and Remote 2 temperature controls PWMx.
110 = fastest speed calculated by all three temperature channel controls PWMx.
111 = manual mode. PWM duty cycle registers (Reg. 0x30 to Reg. 0x32) become
writable.
1
These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Rev. 3 | Page 70 of 81 | www.onsemi.com
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