参数资料
| 型号： | ADT7468ZEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 24/81页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADT7468 |
| 标准包装： | 1 |
| 其它名称： | EVAL-ADT7468EB EVAL-ADT7468EB-ND |
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ADT7468
Figure 28 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. This ensures that an out-
of-limit event cannot be missed, if software is polling the device
periodically. Note that the SMBALERT output remains low for
the entire duration that a reading is out-of-limit and until the
status register has been read. This has implications on how
software handles the interrupt.
Handling SMBALERT Interrupts
To prevent the system from b eing tied up servicing interrupts, it
is recommend to handle the SMBALERT interrupt as follows:
Figure 29. How Masking the Interrupt Source Affects SMBALERT Output
Interrupt Mask Register 1 (Reg. 0x74)
Bit 7 (OOL) = 1, masks SMBALERT for any alert condition
flagged in Status Register 2.
Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.
Bit 5 (LT) = 1, masks SMBALERT for local temperature.
Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.
Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel.
Bit 2 (V CC ) = 1, masks SMBALERT for V CC channel.
Bit 0 (V CCP ) = 1, masks SMBALERT for V CCP channel.
Interrupt Mask Register 2 (Reg. 0x75)
1.
2.
3.
4.
5.
6.
7.
Detect the SMBALERT assertion.
Enter the interrupt handler.
Read the status registers to identify the interrupt source.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Reg. 0x74 and
Reg. 0x75).
Take the appropriate action for a given interrupt source.
Exit the interrupt handler.
Periodically poll the status registers. If the interrupt status
bit has cleared, reset the corresponding interrupt mask bit
Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.
Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.
Bit 5 (FAN4) = 1, masks SMBALERT for Fan 4 failure.
If the T ACH4 pin i s being used as the THERM input, this bit
masks SMBALERT for a THERM event.
Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.
Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.
Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.
Bit 1 (OVT) = 1, masks SMBALERT for overtemperature
(exceeding THERM temperature limits).
Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or for
to 0. This causes the SMBALERT output and status bits to
behave as shown in Figure 29.
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Addresses 0x74
and 0x75. These allow individual interrupt sources to be
masked out to prevent SMBALERT interrupts. Note that
a VID code change, depending on the function used.
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default.
Pin 10 or Pin 14 can be reconfigured as an SMBALERT output
to signal out-of-limit conditions.
Table 12. Configuring Pin 10 a s SMBALERT Output
masking an interrupt source prevents only the SMBALERT
output from being asserted; the appropriate status bit is set
normally.
Register
Configuration Register 3
(Reg. 0x78)
Bit Setting
<0> Pin 10 = alert
<1> Pin 10 = PWM2
HIGH LIMIT
TEMPERATURE
“STICKY”
CLEARED ON READ
(TEMP BELOW LIMIT)
Assigning THERM Functionality to a Pin
Pin 14 on th e ADT7468 has four possible functions:
SMBALERT, THERM, GPIO, and TACH4. The user chooses
the required functionality by setting Bit 0 and Bit 1 of
Configuration Register 4 at Address 0x7D.
STATUS BIT
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
SMBALERT
INTERRUPT
MASK BIT SET
INTERRUPT MASK BIT
CLEARED
(SMBALERT REARMED)
Rev. 3 | Page 24 of 81 | www.onsemi.com
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