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参数资料
| 型号： | B900M24FXX12IT |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQCC44 |
| 文件页数： | 16/100页 |
| 文件大小： | 1547K |
| 代理商： | B900M24FXX12IT |
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22
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
4 Hardware Architecture (continued)
4.2
DSP1600 Core Architectural Overview
(continued)
4.2.1 System Cache and Control Section (SYS)
This section of the core contains a 15-word cache
memory and controls the instruction sequencing. It
handles vectored interrupts and traps and also pro-
vides decoding for registers outside of the DSP1600
core. SYS sequences downloading through JTAG of
self-test programs to internal DPRAM.
The cache loop iteration count can be specified at run
time under program control as well as at assembly
time.
4.2.2 Data Arithmetic Unit (DAU)
The data arithmetic unit (DAU) contains a 16 x 16 par-
allel multiplier that generates a full 32-bit product in
one instruction cycle. The product can be accumulated
with one of two 36-bit accumulators. The accumulator
data can be directly loaded from, or stored to, memory
in two 16-bit words with optional saturation on overflow.
The arithmetic logic unit (ALU) supports a full set of
arithmetic and logical operations on either 16-bit or
32-bit data. A standard set of flags can be tested for
conditional ALU operations, branches, and subroutine
calls. This procedure allows the processor to perform
as a powerful 16-bit or 32-bit microprocessor for logical
and control operations.
The user also has access to two additional DAU regis-
ters. The psw register contains status information from
the DAU. The arithmetic control register, auc, is used
to configure some of the features of the DAU.
4.2.3 Y Space Address Arithmetic Unit (YAAU)
The YAAU supports high-speed, register-indirect, com-
pound, and direct addressing of data (Y) memory. Four
general-purpose 16-bit pointer registers, r0 to r3, are
available in the YAAU. These registers can be used to
supply the read or write addresses for Y space data.
The YAAU also decodes the 16-bit data memory
address and outputs individual memory enables for the
data access. The YAAU can address the internal
DPRAM.
Two 16-bit registers, rb and re, allow zero-overhead
modulo addressing of data for efficient filter implemen-
tations. Two 16-bit signed registers, j and k, are used
to hold user-defined postmodification increments.
Fixed increments of +1, –1, and +2 are also available.
Four compound addressing modes are provided to
make read/write operations more efficient.
The YAAU allows direct (or indexed) addressing of data
memory. In direct addressing, the 16-bit base register
(ybase) supplies the 11 most significant bits of the
address. The direct data instruction supplies the
remaining 5 bits to form a Y space memory address
and also specifies one of 16 registers for source or
destination.
4.2.4 X Space Address Arithmetic Unit (XAAU)
The XAAU supports high-speed, register-indirect
instruction/coefficient memory addressing with post-
modification of the register. The pt register is used for
addressing coefficients. The signed register i holds a
user-defined postincrement. A fixed postincrement of
+1 is also available. Register PC is the program
counter. Registers pr and pi hold the return address
for subroutine calls and interrupts, respectively.
All of the XAAU registers and the adder for increments
are 16 bits wide. The XAAU decodes the 16-bit instruc-
tion/coefficient address and produces signals for the
appropriate X memory segment. The addressable X
segments are internal ROM and internal DPRAM.
The locations of these memory segments depend
upon the memory map selected. A security mode can
be selected by mask option. This prevents unautho-
rized access to the contents of internal ROM.
4.3
Interrupts, Trap, and Low-Power
Standby Mode
The B900 supports vectored interrupts and a trap. The
device has eight internal hardware sources of program
interrupt and one external interrupt pin. As shown in
Table 11 on page 23, each source of an interrupt and
trap has been assigned a unique vector address.
Vectored interrupts are enabled in the inc register (see
Table 42 on page 54) and monitored in the ins register
(see Table 43 on page 54).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| B901 | 制造商:EDAL 制造商全称:EDAL 功能描述:Silicon Bridge Rectifier |
| B901 10.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 10.0MM |
| B901 4.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 4.0MM |
| B901 5.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 5.0MM |
| B901 8.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 8.0MM |
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