参数资料
型号: B900M24FXX12IT
元件分类: 数字信号处理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件页数: 81/100页
文件大小: 1547K
代理商: B900M24FXX12IT
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
Lucent Technologies Inc.
81
8 Timing Requirements and Characteristics (continued)
8.5
Interrupt
5-4018.a
* CLKFREE is the free-running clock sourced to DOUT.
Figure 15. Interrupt Timing Diagram
Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.
Table 104. Timing Requirements for Interrupt
Ref
Parameter
B900
Unit
VDD = 4.5 V to 5.5 V
VDD = 3.0 V to 3.6 V
TMIN = 12.5 ns
TMIN = 16.7 ns
Min
Max
Min
Max
t18*
* Only necessary for synchronized timing; no requirement for asynchronous assertion.
Interrupt Setup (low to low)
17
17
ns
t19
INTB Assertion Time (low to high)
2T
2T
ns
t20
In general, INTB deassertion time should be long enough to allow for the interrupt service routine to be completed.
Note: T = the period of the free-running clock, CLKFREE.
INTB Deassertion Time (high to low)
2T
2T
ns
CLKFREE*
INTB
t18
VOH
VOL
VIH
VIL
t20
t19
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