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参数资料
| 型号： | B900M24FXX12IT |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 59.88 MHz, OTHER DSP, PQCC44 |
| 文件页数： | 22/100页 |
| 文件大小： | 1547K |
| 代理商： | B900M24FXX12IT |
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28
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
4 Hardware Architecture (continued)
4.5
Clock Generation (continued)
4.5.2 Core Clock Switching
When any of the smooth MUX control bits are changed, because of synchronization issues, a delay is incurred
before the clock switch takes place. Five conditional flags can be checked via software to determine when the clock
change actually takes place. These five conditionals are pllon, plloff, slowon, slowoff, stopclk. These five flags indi-
cate that:
s
CLKPLL currently is or is not the output of the smooth MUX.
s
CLKLOW currently is or is not the output of the smooth MUX.
s
STOPCLK main clock for B900 core turned off.
When the SELCLK control bits (clkc[5:4]) are changed, resulting in the smooth MUX switching the source for the
core clock, there is a maximum time for the clock switch to occur (see Table 15). The latencies are defined in terms
of input clock cycles (CLKIN period) and/or low-frequency clock cycles (CLKLOW period). In addition, a stabilization
time is required for the entire clock path of the new source clock before that clock is selected via the SELCLK con-
trol bits (see Table 16).
Table 15. Clock Switch Latencies
Source Clock
Before Switch
Source Clock
After Switch
Maximum Clock Cycles for Switch
CLKIN
CLKPLL
[((N + 1)
2.5) + ((K + 1)/(M + 2)) + 1.5]CLKIN Period
CLKIN
CLKLOW
1.5 CLKLOW Period
CLKIN
CLKCORE2X stopped
1.5 CLKIN Period
CLKLOW
CLKIN
1.5 CLKLOW Period + 1.5 CLKIN Period
CLKLOW
CLKPLL
[((N + 1)
2.5) + ((K + 1)/(M + 2)) + 1.5]CLKIN Period +
1.5 CLKLOW Period
CLKLOW
CLKCORE2X stopped
1.5 CLKLOW Period
CLKPLL
CLKIN
[((N + 1)
3) + 0.5](CLKIN Period)
CLKPLL
CLKLOW
1.5 CLKLOW Period
CLKPLL
CLKCORE2X stopped
[((N + 1)
2.5) + ((K + 1)/(M + 2)) + 1.5]CLKIN Period
CLKCORE2X stopped
CLKIN
1.5 CLKIN Period
CLKCORE2X stopped
CLKLOW
1.5 CLKLOW Period
CLKCORE2X stopped
CLKPLL
[((N + 1)
2.5) + ((K + 1)/(M + 2)) + 1.5]CLKIN Period
Table 16. Core Clock Stabilization Requirements
Source Clock to Be Selected
Condition
Required Stabilization Time Prior
to Selecting Source Clock
CLKIN*
* Assumes that OSCBYP = 0.
Oscillator just enabled
10 ms (preliminary)
CLKRING
Ring oscillator just enabled
100
s (preliminary)
CLKPLL
PLL just enabled
50
s (preliminary)
CLKPLL
Any change to pllc register bits
50
s (preliminary)
CLKLOW
Any change to SLOWMUX[1:0] bits
1 instruction cycle
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| B900J24FXX12IT | 0-BIT, 59.88 MHz, OTHER DSP, PQFP44 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| B901 | 制造商:EDAL 制造商全称:EDAL 功能描述:Silicon Bridge Rectifier |
| B901 10.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 10.0MM |
| B901 4.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 4.0MM |
| B901 5.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 5.0MM |
| B901 8.0MM | 制造商:DORMER TOOLS 功能描述:M/C REAMER B901 8.0MM |
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