参数资料
型号: B900M24FXX12IT
元件分类: 数字信号处理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件页数: 73/100页
文件大小: 1547K
代理商: B900M24FXX12IT
74
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
7 Electrical Requirements and Characteristics (continued)
* Lock-in time represents the time following assertion of the PLLEN bit of the pllc register during which the PLL output clock is unstable. The
B900 must operate from the CLKIN input clock or from CLKLOW while the PLL is locking.
7.1
Typical Power Dissipation
Power dissipation is highly dependent on program activity and the frequency of operation. Table 95 lists typical
power dissipation on a module-by-module basis and consists of preliminary data that is subject to change. For ana-
log modules, this data assumes the recommended external circuitry is being used. For digital modules, it refers to
internal power only, i.e., Table 95 does not account for activity on digital I/O pins. The total analog and internal digi-
tal power can be calculated by adding the sum of the modules that have been enabled. For example, the lowest
power dissipation can be achieved by turning everything off except for the internal low-power oscillator and setting
the stop-clock bit. In this case, the total power would be 62 W at 3.1 V.
Table 93. PLL Electrical Specifications, VCO Frequency Ranges
Parameter
Symbol
Min
Max
Unit
VCO Frequency Range*:
VDD = 3 V
± 10%
VDD = 5 V
± 10%
* The M and N counter values in the pllc register must be set so that the VCO will operate in the appropriate range,
where
.
Choose the lowest value of N and then the appropriate value of M for internal MIPS rate =
fVCO
50
150
200
MHz
Input Jitter at CKI
200
ps-rms
Table 94. PLL Electrical Specifications and Register Settings
Voltage
(Volts)
M
pllc[5:0]
K
pllc[8:6]
N
pllc[10:9]
ICP
pllc[13:11]
LF
pllc[15:14]
PFIVOLT
clkc[12]
Typical Lock
Time (s)*
3.0—3.6
>28
0—7
0—1
101
11
0
8—20
3.0—3.6
19—28
0—7
0—1
110
10
0
8—20
3.0—3.6
<19
0—7
0—1
110
01
0
8—20
4.5—5.5
>28
0—7
0—1
110
11
1
8—20
4.5—5.5
19—28
0—7
0—1
111
10
1
8—20
4.5—5.5
<19
0—7
0—1
111
01
1
8—20
VC Ofreq
CLKINfreq
m2
+
()
N1
+
()
-----------------
×
=
I
( nputClock m 2 )
+
()
2K
(
1
) N1 ))
+
(
+
(
----------------------------------------------------------
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