参数资料
型号: B900M24FXX12IT
元件分类: 数字信号处理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件页数: 77/100页
文件大小: 1547K
代理商: B900M24FXX12IT
78
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
8 Timing Requirements and Characteristics (continued)
8.2
B900 Clock Generation
5-4009.a
* Input clock; the DOUT pin may be selected to be the input clock, see the clkc register.
Figure 12. I/O Clock Timing Diagram
Note: For Tables 95 to 114, TMIN is the minimum instruction cycle time (see Section 8.1 on page 77).
Table 99. Timing Requirements for Input Clock
Ref
Parameter
B900
Unit
VDD = 4.5 V to 5.5 V
VDD = 3.0 V to 3.6 V
TMIN = 12.5 ns
TMIN = 16.7 ns
Min
Max
Min
Max
t1*
* The clock input frequency should normally be set to 4.096 MHz for proper PLL operation.
Clock In Period (low to low)
12.5
Device is fully static; t1 is tested at 125 ns, and memory hold time is tested at 0.1 s.
16.7
ns
t2
Clock In Low Time (low to high)
6
8
ns
t3
Clock In High Time (high to low)
6
8
ns
Table 100. Timing Requirements for Input Clock and Output Clock
Ref
Parameter
B900
Unit
VDD = 4.5 V to 5.5 V
VDD = 3.0 V to 3.6 V
TMIN = 12.5 ns
TMIN = 16.7 ns
Min
Max
Min
Max
t4
Clock Out High Delay (high to high)
21
21
ns
t5
Clock Out Low Delay (low to low)
21
21
ns
t6
Clock Out Period (high to low)
12.5
12.5
ns
t4
t6
t1
t2
XTALA
VIH
VIL
t5
DOUT = CLKIN*
t3
VOL
VOH
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