参数资料
型号: B900M24FXX12IT
元件分类: 数字信号处理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件页数: 33/100页
文件大小: 1547K
代理商: B900M24FXX12IT
38
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
4 Hardware Architecture (continued)
4.11 Bit Manipulation Unit (BMU)
The BMU interfaces directly to the main accumulators in the DAU providing the following features:
s
Barrel shifting—logical and arithmetic, left and right shift
s
Normalization and extraction of exponent
s
Bit-field extraction and insertion
These features increase the efficiency of the B900 in applications such as control or data encoding and decoding.
For example, data packing and unpacking, in which short data words are packed into one 16-bit word for more effi-
cient memory storage, is very easy.
In addition, the BMU provides two auxiliary accumulators, aa0 and aa1. In one instruction cycle, 36-bit data can be
shuffled, or swapped, between one of the main accumulators and one of the alternate accumulators. The ar<0—3>
registers are 16-bit registers that control the operations of the BMU. They store a value that determines the amount
of shift or the width and offset fields for bit extraction or insertion. Certain operations in the BMU set flags in the
DAU psw register and the alf register. See Table 48 on page 57 and Table 36 on page 49. The ar<0—3> registers
can also be used as general-purpose registers.
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