参数资料
型号: B900M24FXX12IT
元件分类: 数字信号处理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件页数: 44/100页
文件大小: 1547K
代理商: B900M24FXX12IT
48
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
5 Software Architecture (continued)
5.1
Instruction Set (continued)
5.1.8 Data Move Instructions
Table 34 shows data move instructions and their required numbers of program-memory words and instruction
cycles. All data move instructions, except those doing long immediate loads, can be executed from within the cache.
A direct data addressing mode has been added to the DSP1600 core.
When signed registers less than 16 bits wide (c0, c1, c2) are read, their contents are sign-extended to
16 bits. When unsigned registers less than 16 bits wide are read, their contents are zero-extended to 16 bits.
Loading an accumulator with a data move instruction does not affect the flags.
Table 34. Data Move Instructions
Data Move
Instructions
Number of
Words
Number of
Cycles
R = IM16
2
SR = IM9
1
aT[l] = R
R = aS[l]
Y = R
R = Y
Z:R
DR = *(OFFSET)
*(OFFSET) = DR
12
Table 35. Replacement Table for Data Move Instructions
Replace
Value
Meaning
R
Any of the registers in Table 81 on page 68*
* Some registers are write only or read only.
DR
r<0—3>, a0[l], a1[l], y[l], p[l], x, pt, pr, psw
Subset of registers accessible with direct addressing.
aS, aT
a0, a1
High half of accumulator.
Y
*rM, *rM++, *rM– –, *rM++j
Same as in multiply/ALU instructions.
Z
*rMzp, *rMpz, *rMm2, *rMjk
Same as in multiply/ALU instructions.
IM16
16-bit value
Long immediate data.
IM9
9-bit value
Short immediate data for YAAU registers.
OFFSET
5-bit value from instruction
11-bit value from base register
Value in bits 15:5 of ybase register form the 11 most
significant bits of the base address. The 5-bit offset is
concatenated to this to form a 16-bit address.
SR
r<0—3>, rb, re, j, k
Subset of registers for short immediate data.
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