![](http://datasheet.mmic.net.cn/160000/B900M24FXX12IT_datasheet_8427896/B900M24FXX12IT_34.png)
34
Lucent Technologies Inc.
B900
Advance Data Sheet
Baseband Signal Processor
July 1999
4 Hardware Architecture (continued)
4.10 Dual-Channel Serial I/O Port (SIO) for
B900
The SIO interfaces to the external world through five
pins: serial data input (SDI), serial data output (SDO),
serial clock (SCLK), serial load A (SLDA), and serial
load B (SLDB). The SIO pins are multiplexed with
IOPB pins. When the SIO is enabled, the IOPB[7:4]
pins are configured as SIO pins, i.e., SDI, SDO, SCLK,
and SLDA; otherwise, these pins function normally as
IOP pins. When the SIO is enabled in dual-channel
is configured for SLDB operation; otherwise, this pin
normally functions as the IOPB2 pin.
Serial data enters the SIO through the SDI pin and
exits through the SDO pin. SCLK is the clock that con-
trols shifting data in and out of the SIO. Data is shifted
in and latched on the falling edge of SCLK, while data
is shifted out on the rising edge of SCLK. SLDA and
SLDB provide the strobes necessary for initiating serial
transfers. For single-channel mode, only the SLDA pin
is necessary; however, for dual-channel operation,
SLDA and SLDB initiate transfers from channels A and
B, respectively.
The SIO can be configured to support many serial pro-
tocols; however, all serial transfers are restricted to
most significant bit (MSB) format. That is, the most sig-
nificant bit in the data is always transmitted first. The
serial input/output control (sioc) register configures the
SIO for different transfer modes.
The SIO can be configured to operate in either active
or passive mode, depending on the setting of the
ACTIVE bit. In active mode, the SIO is the master and
controls the serial interface by generating the serial
clock and load pulses. In passive mode, the SIO is the
slave, and control signals are supplied by the external
serial device.
By default, the SIO is configured to support a single
channel; however, the SIO can also be configured in a
dual-channel mode that allows it to support two exter-
nal serial devices. In this mode, serial transfers are
time-division multiplexed between two channels; i.e.,
first serial data is transferred to/from channel A, and
then serial data is transferred to/from channel B. Set-
ting the DUAL bit in the sioc register configures the
SIO for dual-channel operation.
SLDA and SLDB are the strobes that initiate serial
transfers on the corresponding channels. In single-
channel mode, only SLDA is used to initiate serial
transfers. Both SLDA and SLDB can be configured to
assert on either high-to-low or low-to-high transitions
through the LDTA and LDTB bits.
In active mode, SLDA and SLDB can be configured to
be delayed by one SCLK cycle. When the DLP bit is
set, the load pulses occur at the same time as the first
bit is being shifted in and out of the SIO. The DLP bit
has no effect when the SIO is configured for passive-
mode operation.
In active mode, SCLK is selectable between CLKIN
and CLKIN/2. The load pulse frequencies are select-
able as SCLK divided by 256 or 512.