参数资料
型号: B900M24FXX12IT
元件分类: 数字信号处理
英文描述: 0-BIT, 59.88 MHz, OTHER DSP, PQCC44
文件页数: 67/100页
文件大小: 1547K
代理商: B900M24FXX12IT
Lucent Technologies Inc.
69
Advance Data Sheet
B900
July 1999
Baseband Signal Processor
5 Software Architecture (continued)
5.4
Instruction Set Formats (continued)
5.4.6 Field Descriptions (continued)
R/W Field: A 1 specifies a read, DR = *(OFFSET).
A 0 specifies a write, *(OFFSET) = DR.
S Field: Specifies a source accumulator.
SI Field: Specifies when the conditional branch
qualifier instruction should be interpreted as a software
interrupt instruction. (Reserved for Lucent hardware
development system use.)
SRC2 Field: Specifies operands in an F3 ALU
instruction.
X Field: Specifies the addressing of ROM data in the
two-operand multiply/ALU instructions. Specifies the
high or low half of an accumulator or the y register in
one-operand multiply/ALU instructions.
Y Field: Specifies the form of register-indirect
addressing with postmodification.
Z Field: Specifies the form of register-indirect
compound addressing with postmodification.
Table 82. S Field
SRegister
0
Accumulator 0
1
Accumulator 1
Table 83. SI Field
SI
Operation
0
Not a software interrupt
1
Software interrupt
Table 84. SRC2 Field
SRC2
Operands
00
aSl, IM16
10
aSh, IM16
01
aS, aT
11
aS, p
Table 85. X Field
X
Operation
Two-Operand Multiply/ALU
0
1
*pt++
*pt++i
One-Operand Multiply/ALU
0
1
aTl, yl
aTh, yh
Table 86. Y Field
Y
Operation
0000
0001
0010
0011
*r0
*r0++
*r0– –
*r0++j
0100
0101
0110
0111
*r1
*r1++
*r1– –
*r1++j
1000
1001
1010
1011
*r2
*r2++
*r2– –
*r2++j
1100
1101
1110
1111
*r3
*r3++
*r3– –
*r3++j
Table 87. Z Field
Z
Operation
0000
0001
0010
0011
*r0zp
*r0pz
*r0m2
*r0jk
0100
0101
0110
0111
*r1zp
*r1pz
*r1m2
*r1jk
1000
1001
1010
1011
*r2zp
*r2pz
*r2m2
*r2jk
1100
1101
1110
1111
*r3zp
*r3pz
*r3m2
*r3jk
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