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| 型号： | DSP56301VF100 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 13/124页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT FIXED-POINT 252-BGA |
| 产品变化通告： | DSP56301 Discontinuation 12/Nov/2009 |
| 标准包装： | 60 |
| 系列： | DSP563xx |
| 类型： | 定点 |
| 接口： | 主机接口，SSI，SCI |
| 时钟速率： | 100MHz |
| 非易失内存： | ROM（9 kB） |
| 芯片上RAM： | 24kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 252-BGA |
| 供应商设备封装： | 252-MAPBGA（21x21） |
| 包装： | 托盘 |
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External Memory Expansion Port (Port A)
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-7
1.5.3
External Bus Control
Table 1-8.
External Bus Control Signals
Signal Name
Type
State During
Reset
Signal Description
AA0/RAS0–
AA3/RAS3
Output
Tri-stated
Address Attribute or Row Address Strobe
As AA, these signals function as chip selects or additional address lines.
Unlike address lines, however, the AA lines do not hold their state after a read
or write operation. As RAS, these signals can be used for Dynamic Random
Access Memory (DRAM) interface. These signals have programmable
polarity.
RD
Output
Tri-stated
Read Enable
When the DSP is the bus master, RD is asserted to read external memory on
the data bus (D[0–23]). Otherwise, RD is tri-stated.
WR
Output
Tri-stated
Write Enable
When the DSP is the bus master, WR is asserted to write external memory on
the data bus (D[0–23]). Otherwise, WR is tri-stated.
TA
Input
Ignored Input
Transfer Acknowledge
If the DSP56301 is the bus master and there is no external bus activity, or the
DSP56301 is not the bus master, the TA input is ignored. The TA input is a
Data Transfer Acknowledge (DTACK) function that can extend an external bus
cycle indefinitely. Any number of wait states (1, 2,..., infinity) can be added to
the wait states inserted by the BCR by keeping TA deasserted. In typical
operation, TA is deasserted at the start of a bus cycle, asserted to enable
completion of the bus cycle, and deasserted before the next bus cycle. The
current bus cycle completes one clock period after TA is asserted
synchronous to CLKOUT. The number of wait states is determined by the TA
input or by the Bus Control Register (BCR), whichever is longer. The BCR can
set the minimum number of wait states in external bus cycles.
To use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion;
otherwise improper operation may result. TA can operate synchronously or
asynchronously, depending on the setting of the TAS bit in the Operating
Mode Register (OMR).
TA functionality cannot be used during DRAM-type accesses; otherwise
improper operation may result.
BR
Output
(deasserted)
Bus Request
Asserted when the DSP requests bus mastership and deasserted when the
DSP no longer needs the bus. BR can be asserted or deasserted
independently of whether the DSP56301 is a bus master or a bus slave. Bus
“parking” allows BR to be deasserted even though the DSP56301 is the bus
master (see the description of bus “parking” in the BB signal description). The
Bus Request Hole (BRH) bit in the BCR allows BR to be asserted under
software control, even though the DSP does not need the bus. BR is typically
sent to an external bus arbitrator that controls the priority, parking and tenure
of each master on the same external bus. BR is affected only by DSP requests
for the external bus, never for the internal bus. During hardware reset, BR is
deasserted and the arbitration is reset to the bus slave state.
BG
Input
Ignored Input
Bus Grant
Must be asserted/deasserted synchronous to CLKOUT for proper operation.
An external bus arbitration circuit asserts BG when the DSP56301 becomes
the next bus master. When BG is asserted, the DSP56301 must wait until BB
is deasserted before taking bus mastership. When BG is deasserted, bus
mastership is typically given up at the end of the current bus cycle. This may
occur in the middle of an instruction that requires more than one external bus
cycle for execution.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56301VF80 | 功能描述:数字信号处理器和控制器 - DSP, DSC MAP DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56301VF80B1 | 功能描述:数字信号处理器和控制器 - DSP, DSC DSP56301VF80B1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSP56301VL100 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:24-Bit Digital Signal Processor |
| DSP56301VL80 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:24-Bit Digital Signal Processor |
| DSP56302 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:DSP56301 Digital Signal Processor |
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