参数资料
型号: DSP56301VF100
厂商: Freescale Semiconductor
文件页数: 80/124页
文件大小: 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
产品变化通告: DSP56301 Discontinuation 12/Nov/2009
标准包装: 60
系列: DSP563xx
类型: 定点
接口: 主机接口,SSI,SCI
时钟速率: 100MHz
非易失内存: ROM(9 kB)
芯片上RAM: 24kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 252-BGA
供应商设备封装: 252-MAPBGA(21x21)
包装: 托盘
AC Electrical Characteristics
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-33
The asynchronous bus arbitration is enabled by internal BB inputs and synchronization circuits on BG. These
synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this
delay, a DSP56300 part can assume mastership and assert BB, for some time after BG is deasserted. Timing 250
defines when BB can be asserted.
Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is exposed to other
DSP56300 components which are potential masters on the same bus. If BG input is asserted before that time, a
situation of BG asserted, and BB deasserted, can cause another DSP56300 component to assume mastership at the
same time. Therefore, a non-overlap period between one BG input active to another BG input active is required.
Timing 251 ensures that such a situation is avoided.
2.5.6
Host Interface Timing
Figure 2-26.
Asynchronous Bus Arbitration Timing
Table 2-18.
Universal Bus Mode Timing Parameters
No.
Characteristic
Expression
80 MHz
100 MHz
Unit
Min
Max
Min
Max
300
Access Cycle Time
3
× TC
37.5
30.0
ns
301
HA[10–0], HAEN Setup to Data Strobe Assertion1
5.8
4.6
ns
302
HA[10–0], HAEN Valid Hold from Data Strobe Deassertion1
0.0
0.0
ns
303
HRW Setup to HDS Assertion2
5.8
4.6
ns
304
HRW Valid Hold from HDS Deassertion2
0.0
0.0
ns
305
Data Strobe Deasserted Width1
4.1
3.3
ns
306
Data Strobe Asserted Pulse Width1
80 MHz: 2.5
× TC + 1.7
100 MHz: 2.5
× TC + 1.3
32.9
26.3
ns
307
HBS Asserted Pulse Width
2.5
2.0
ns
308
HBS Assertion to Data Strobe Assertion1
80 MHz: TC 4.9
100 MHz: TC 4.0
—7.6
—6.0
ns
309
HBS Assertion to Data Strobe Deassertion1
80 MHz: 2.5
× TC + 2.9
100 MHz: 2.5
× TC + 2.3
34.1
27.3
ns
310
HBS Deassertion to Data Strobe Deassertion1
80 MHz: 1.5
× TC + 3.3
100 MHz: 1.5
× TC + 2.6
22.1
17.6
ns
311
Data Out Valid to TA Assertion (HBS Not Used—Tied to VCC)
2
80 MHz: 2
× TC 11.6
100 MHz: 2
× TC 9.2
13.4
10.8
ns
312
Data Out Active from Read Data Strobe Assertion3
1.7
1.3
ns
BG1
BB
251
BG2
250
250+251
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