参数资料
型号: DSP56301VF100
厂商: Freescale Semiconductor
文件页数: 94/124页
文件大小: 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
产品变化通告: DSP56301 Discontinuation 12/Nov/2009
标准包装: 60
系列: DSP563xx
类型: 定点
接口: 主机接口,SSI,SCI
时钟速率: 100MHz
非易失内存: ROM(9 kB)
芯片上RAM: 24kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 252-BGA
供应商设备封装: 252-MAPBGA(21x21)
包装: 托盘
AC Electrical Characteristics
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-45
Notes:
1.
For the internal clock, the external clock cycle is defined by the instruction cycle time (timing 7 in Table 2-5 on page 2-6) and
the ESSI control register.
2.
The word-relative frame sync signal waveform relative to the clock operates the same way as the bit-length frame sync signal
waveform, but spreads from one serial clock before the first bit clock (same as Bit Length Frame Sync signal), until the one
before the last bit clock of the first word in frame.
3.
Periodically sampled and not 100 percent tested
4.
VCC = 3.3 V ± 0.3 V; TJ = 40°C to +100 °C, CL = 50 pF
5.
TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) Receive Frame Sync
6.
i ck = Internal Clock
x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode
(Asynchronous implies that TXC and RXC are two different clocks)
i ck s = Internal Clock, Synchronous Mode
(Synchronous implies that TXC and RXC are the same clock)
7.
bl = bit length
wl = word length
wr = word length relative
8.
If the DSP core writes to the transmit register during the last cycle before causing an underrun error, the delay is 20 ns + (0.5
×
TC).
Table 2-22.
ESSI Timings (Continued)
No.
Characteristics4, 5, 7
Symbol
Expression
80 MHz
100 MHz
Cond-
ition6
Unit
Min
Max
Min
Max
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