参数资料
型号: DSP56301VF100
厂商: Freescale Semiconductor
文件页数: 82/124页
文件大小: 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
产品变化通告: DSP56301 Discontinuation 12/Nov/2009
标准包装: 60
系列: DSP563xx
类型: 定点
接口: 主机接口,SSI,SCI
时钟速率: 100MHz
非易失内存: ROM(9 kB)
芯片上RAM: 24kB
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 252-BGA
供应商设备封装: 252-MAPBGA(21x21)
包装: 托盘
DSP56301 Technical Data, Rev. 10
2-34
Freescale Semiconductor
Specifications
313
Data Out Valid from Read Data Strobe Assertion
(No Wait States Inserted—HTA Asserted)3
18.9
16.9
ns
314
Data Out Valid Hold from Read Data Strobe Deassertion3
1.7
1.3
ns
315
Data Out High Impedance from Read Data Strobe Deassertion3
12.0
9.6
ns
316
Data In Valid Setup to Write Data Strobe Deassertion4
8.3
6.6
ns
317
Data In Valid Hold from Write Data Strobe Deassertion4
0.0
0.0
ns
318
HSAK Assertion from Data Strobe Assertion1
30.0
30.0
ns
319
HSAK Asserted Hold from Data Strobe Deassertion1
2.0
2.0
ns
320
HTA Active from Data Strobe Assertion1,2,5
3.1
2.5
ns
321
HTA Assertion from Data Strobe Assertion
(HBS Not Used—Tied to VCC)
1,2,5
80 MHz: 2.0
× TC + 13.0
100 MHz: 2.0
× TC + 12.2
38.0
32.2
ns
322
HTA Assertion from HBS Assertion2,5
80 MHz: 2.0
× TC + 13.0
100 MHz: 2.0
× TC + 12.2
38.0
32.2
ns
323
HTA Deasserted from Data Strobe Assertion1,2,5
17.1
15.0
ns
324
HTA Assertion to Data Strobe Deassertion1,2
0.0
0.0
ns
325
HTA High Impedance from Data Strobe Deassertion1,2
15.3
12.2
ns
326
HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
(LT + 1)
× TC 6.07
19.0
14.0
ns
327
Data Strobe Deasserted Hold from HIRQ Deassertion
(HIRH = 0)1
0.0
0.0
ns
328
HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)1
1.5
× TC
18.8
15.0
ns
329
HIRQ Deassertion from Data Strobe Assertion
(HIRH = 1, HIRD = 1)1
80 MHz: 2.5
× TC + 24.7
100 MHz: 2.5
× TC + 21.5
55.9
46.5
ns
330
HIRQ High Impedance from Data Strobe Assertion
(HIRH = 1, HIRD = 0)1,6
80 MHz: 2.5
× TC + 24.7
100 MHz: 2.5
× TC + 21.5
55.9
46.5
ns
331
HIRQ Active from Data Strobe Deassertion
(HIRH = 1, HIRD = 0)1
2.5
× TC
31.3
25.0
ns
332
HIRQ Deasserted Hold from Data Strobe Deassertion1
2.5
× TC
31.3
25.0
ns
333
HDRQ2 Asserted Hold from Data Strobe Assertion1
1.5
× TC
18.8
15.0
ns
334
HDRQ2 Deassertion from Data Strobe Assertion1
80 MHz: 2.5
× TC + 24.7
100 MHz: 2.5
× TC + 21.5
55.9
46.5
ns
335
HDRQ2 Deasserted Hold from Data Strobe Deassertion1
80 MHz: 2.5
× TC + 3.7
100 MHz: 2.5
× TC + 3.0
35.0
28.0
ns
336
HDAK Assertion to Data Strobe Assertion1
5.8
4.6
ns
337
HDAK Asserted Hold from Data Strobe Deassertion1
0.0
0.0
ns
338
HDBEN Deasserted Hold from Data Strobe Assertion1
2.5
2.0
ns
339
HDBEN Assertion from Data Strobe Assertion1
22.2
19.6
ns
340
HDBEN Asserted Hold from Data Strobe Deassertion1
2.5
2.0
ns
341
HDBEN Deassertion from Data Strobe Deassertion1
22.2
19.6
ns
342
HDBDR High Hold from Read Data Strobe Assertion3
2.5
2.0
ns
343
HDBDR Low from Read Data Strobe Assertion3
22.2
19.6
ns
344
HDBDR Low Hold from Read Data Strobe Deassertion3
2.5
2.0
ns
Table 2-18.
Universal Bus Mode Timing Parameters (Continued)
No.
Characteristic
Expression
80 MHz
100 MHz
Unit
Min
Max
Min
Max
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