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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 13/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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13
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
3. EXTERNAL INTERFACES
The external interfaces provided on the IDT88P8344 device are four SPI-
3 interfaces, one SPI-4 interface, a serial or parallel mcroprocessor interface,
a JTAG interface, and a set of GPIO pins. Each of the interfaces is defined in the
relevant standard.
The following information contains a set of the highlights of the features
supported fromthe relevant standards, and a description of additional features
implemented to enhance the usability of these interfaces for the systemarchitect.
3.1 SPI-3
Refer to OIF SPI-3 document (see 13.Glossary for a reference) for full details
of the implementation agreement.
- Four instantiations of SPI-3 interface; each interface independently
configurable
- Device supports a 8-bit and 32-bit data bus structure.
- Clock rate is mnimum19.44 to maximum133 MHz
- Link, single port PHY, and single device multi port PHY modes supported
- Byte level and packet level transfer control mechanisms supported
Four DTPA signals supported, mapped to LP addresses 0 – 3, for STPA
in byte-level mode
Eight ADR signals supported for PTPA in packet-level mode
- Address range 0 to 255 with support for 64 simultaneously active logical ports
- Fragment length (section) configurable from16 to 256 bytes in 16 byte
multiples
- Configurable standard and non-standard bit ordering
SPI-3 implementation features
The following are implemented per SPI-3 interface, and there are four
instantiations per device.
- Link / PHY layer device
- Packet / byte level FIFO status information
- Physical port enable
- Width of data bus (32 bit or 8 bit)
- Parity selection (odd or even)
- Enable parity check
3.1.1 SPI-3 ingress
The following are implemented per SPI-3 interface, and there are 4
instantiations per device.
- SPI-3 LP to Link Identifier (LID) map
- 256 entries, one per SPI-3 LP address
- LP enable control
- Only 64 of these entries are to be in the active state simultaneously
Backpressure enable
- Link mode only
- Enables the assertion of the I_ENB when at least one active LID can not
accept data
- If not enabled, the I_ENB signal will never be asserted in Link mode, possibly
leading to fragments being discarded.
Minimum packet length
- Packets shorter than the mnimumlength will be optionally counted in the
short packet counter.
- Range 0 – 255 in 1 byte increments
Maximum packet length
- Packets longer than the maximumlength will be optionally counted in the
long packet counter.
- Range 0 – 16,383 in 1 byte increments
Backpressure threshold
- Number of free segments allocated below which backpressure will be
triggered for the LP
SPI-3 ingress interface
Multiple independent data streams can be transmtted over the physical SPI-
3 port. Each of those data streams is identified by a SPI-3 logical port ( LP ). Data
froma transfer on a SPI-3 logical port and the associated descriptor fields are
synchronized to the configurable internal buffer segment pool.
Normal operation
Refer to [13. Glossary] for details about the SPI-3 interface.
A SPI-3 interface ( a physical port ) is enabled by the SPI-3_ENABLE flag
in the SPI-3 configuration register. A disabled interface tri-states all output
pins and does not respond to any input signals.
The interface is configured in PHY or Link layer mode by the LINK flag
in the SPI-3 general configuration register.
The interface supports a SPI-3 logical port number range [0..255], note that
at most 64 logical ports can be configured.
The SPI-3 interface supports data transport over either a 32 bit data
interface or over one single 8 bit interface (data[7:0] ) only. The selection
is defined by the BUSWIDTH flag in the SPI-3 general configuration register.
The SPI-3 interface is configured in byte mode or packet mode by the
PACKET flag in the SPI-3 general configuration register.
The SPI-3 interface supports over-clocking.
Parity checking over data[31:0] is enabled by the PARITY_EN flag in the
Table 50, SPI-3 general configuration register (register_offset=0x00). The
parity type is defined by the EVEN_PARITY flag. Parity check results over
the in-band port address and the data of a transfer are forwarded towards
the packet fragment processor.
SPI Exchange supports zero clock interval spacing between transfers.
SPI-3 ingress interface errors
Given an I_FCLK within specification, the SPI-3 will not dead lock due to any
combination or sequence on the SPI-3 interface. The SPI Exchange detects for
incorrect SOP / EOP sequences on a logical port. The following sequences are
detected:
Successive SOP ( SOP- SOP sequence rather than SOP –EOP –SOP-EOP )
Successive EOP ( EOP- EOP sequence rather than SOP –EOP –SOP-EOP )
Detection of an illegal sequence results in the generation of an SPI-3 illegal
SOP sequence event or SPI-3 illegal EOP sequence even generated. The
event is associated to the physical port. The event is directed towards the PMON
& DIAG module.
A clock available process detects a positive I_FCLK within a 64 MCLK clock
cycle period. The result of this process is reported in the I_FCLK_AV flag in the
Table 52 SPI-3 ingress fill level register (Block_base 0x0200 + Register_offset
0x02).
A status change fromthe clock available status to the clock not available status
generates a maskable SPI-3 ingress clock unavailable interrupt indication,
SPI3_ICLK_UN, in Table 62-Non LID associated interrupt indication register
(Block_Base 0x0C00 + Register_offset 0x0C).
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