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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 20/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
Normal status information when in the IN_SYNCH state
The normal status information is generated based on ingress buffer full
information and PFP buffer segment fill level.
For information on DIP-2 generation and training pattern refer to the OIF SPI-
4 document [Glossary].
DIP-2 error insertion
A number of consecutive DIP-2 errors can be generated. The I_ DIP_E_NUM
field in Table 97, SPI-4 ingress diagnostics register (register_offset 0x0F)
specifies the number of errors to be generated. A logic one written to
I_ERROR_INS will activate the I_DIP_E_NUMfield and trigger error insertion.
The I_ERROR_INS field self clears when the number of errors have been
generated.
LVTTL and LVDS status interface selection
The LVDS_STA pin selects which FIFO status interface is being used for SPI-
4. HIGH = LVDS status interface, LOW = LVTTL status interface.
3.2.2 SPI-4 egress
The SPI-4 egress includes
Status channel synchronization
Status updating
Data transfer
Periodic training
PFP interface
SPI-4 egress configurable parameters
All parameters as listed in the 0IF SPI-4 document [see Glossary]
CALENDAR_LEN: 4 to 1,024 in increments of 4
CALENDAR_M: 1 to 256 in increments of 1
MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16
MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16
Alpha: 1 to 256 in increments of 1
DATA_MAX_T: 1 to 4,294,967,040 in increments of 1
FIFO_MAX_T: 1 to 16,777,215 in increments of 1
Calendar and shadow calendar
- 256 entries
- E_CSW_EN field in Table 104, SPI-4 egress configuration register_0
(register_offset 0x00) bit for manual reconfiguration swap
Multiple burst enable
- Allows more than one burst to be sent to an LP. Feature included to relieve
systems with long latency between updates.
SPI-4 egress LID to LP map
- 256 entries, one per SPI-4 LP
- Enable bit
Ingress
egress
Out of synch, send status training
In synch, send status frame
In synch, send status frame
Out of synch, send data training
Out of synch, send data training
In synch, send data/idle
3.2.3 SPI-4 startup handshake
Ingress
Egress
Out of synch, send status training
Out of synch, send status training
In synch, send status frame
In synch, send status frame
In synch, send data/idle
Out of synch, send data training
Out of synch, send data training
In synch, send data/idle
TABLE 11 – INGRESS OUT OF SYNCH, EGRESS IN SYNCH
TABLE 10 – BOTH ATTACHED DEVICES START FROM RESET STATUS
Ingress
Egress
In synch, send status frame
Out of synch, send status training
In synch, send status frame
In synch, send status frame
Out of synch, send data training
Out of synch, send data training
Out of synch, send data training
In synch, send data/idle
TABLE 12 – INGRESS IN SYNCH, EGRESS OUT OF SYNCH
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相关代理商/技术参数 |
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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