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参数资料
| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 66/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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66
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
9.3.11 Block base 0x1600 registers
The SPI-4 ingress registers are at Block_base 0x1600.
SPI-4 ingress packet length configuration
(Block_base 0x1600 + Register_offset 0x00-0x3F)
TABLE 79 - SPI-4 INGRESS PACKET LENGTH
CONFIGURATION (64 ENTRIES)
Field
Bits
MIN_LENGTH
7:0
Reserved
15:8
MAX_LENGTH
29:16
Reserved
31:30
There are four sets of 64 registers for SPI-4 ingress packet length configu-
ration, one per SPI-3 interface. Each register has read and write access. The
mnimumand maximumpacket lengths per LID are provisioned using a SPI-
4 ingress packet length configuration register. The bit fields of a SPI-4 ingress
packet length configuration register are described.
MIN_LENGTH
SPI-4 ingress mnimumpacket length. The mnimum
packet length is programmed from0 to 255 bytes. The resolution is one byte.
Length
8
8
14
2
Initial Value
0x40
0x00
0x5EE
0x0
MAX_LENGTH
SPI-4 ingress maximumpacket length. The maximum
packet length is programmed from0 to 16,383 bytes. The resolution is one byte.
9.3.12 Block base 0x1700 registers
SPI-3 egress port descriptor table (Block_base
0x1700 + Register_offset 0x00-0x3F)
TABLE 80 - SPI-3 EGRESS PORT DESCRIPTOR
TABLE (64 ENTRIES)
Field
Bits
MAX_BURST
3:0
Reserved
7:4
DIRECTION
8:9
Reserved
31:10
There are 64 SPI-3 egress port descriptor tables per SPI-3 egress port. The
SPI-3 egress port descriptor table has read and write access. The SPI-3 egress
per LID packet fragment length and direction are provisioned using the SPI-3
egress port descriptor tables. The bit fields of a SPI-3 egress port descriptor table
are described.
MAX_BURST
more than MAX_BURST field multiplied by sixteen is the packet fragment length
for the LP. For example, programmng the number 3 into the MAX_BURST field
results in a packet fragment length of (3+1) x 16 = 64 bytes. The MAX_BURST
field is used to prioritize traffic.
SPI-3 packet fragment length for a SPI-3 egress LP. One
DIRECTION
The Path selection is defined for each of the 64 LIDs by the associated
DIRECTION field as shown in the following table
.
TABLE 81 - SPI-3 EGRESS DIRECTION CODE
ASSIGNMENT
The SPI-3 egress traffic is directed to a SPI-3 egress port.
Length
4
4
2
22
Initial Value
0x0F
0x0
0b11
0x00
9.3.13 Block base 0x1800 registers
SPI-4 ingress port descriptor table (Block_base
0x1800 + Register_offset 0x00-0x3F)
TABLE 82 - SPI-4 INGRESS PORT DESCRIPTOR
TABLE (64 ENTRIES)
Field
Bits
M
8:0
Reserved
15:9
FREE_SEGMENT_S
20:16
Reserved
23:21
FREE_SEGMENT_H
28:24
Reserved
31:29
There is one set of 64 registers for SPI-4 ingress port descriptors per SPI-
3 interface. The SPI-4 ingress port descriptor tables are 32 bits wide and have
read and write access. Each of the SPI-4 ingress port descriptor tables is used
to control the amount of buffering and the backpressure threshold of the available
buffer segment pool for the SPI-4 ingress.
Each SPI-4 ingress buffer segment pool is 128 Kbytes, divided into 508 buffer
segments of 256 bytes per segment. The 508 buffer segments can be shared
among the LIDs initially programmed by the numerical field NR_LID. Of the share
of the buffer memory, a SPI-4 LID can be allocated the maximumnumber of
segments permtted, or can be programmed to fewer segments by decreasing
the Mfield. Decreasing Mincreases the chance of backpressure and possibly
buffer overflow, but can result in lower latency.
The FREE_SEGMENT_S (starving threshold) and FREE_SEGMENT_H
(hungry threshold) fields are used, along with the Mfield, to set the two
backpressure settings per LID on the SPI-4 ingress. The FREE_SEGMENT_S
field must always be greater than the FREE_SEGMENT_H field.
M
The number of 256-byte buffer pool segments allocated to a LID. The
range of Mis 0x000 to 0x1FC (508 base 10), but can not exceed the number
dictated by NR_LID [Block_base 0x1900 + Register_offset 0x00].
FREE_SEGMENT_S
This field is used to define the SPI-4 ingress per-LID starving backpressure
threshold based on the number of free buffer pool segments (M) available, as
follows:
THRESHOLD_S = N * FREE_SEGEMENT_S, where the value of N is
defined as:
DIRECTION
00
01
10
11
Path
SPI-3 physical
Reserved
Capture
Discard
Length
9
7
5
3
5
3
Initial Value
0x000
0x00
0x00
0x0
0x00
0x0
M[8:0]
N
16
8
4
2
1
0x1FF to 0x100
0x0FF to 0x080
0x07F to 0x040
0x03F to 0x020
0x01F to 0x000
FREE_SEGMENT_H
This field is used to define the SPI-4 ingress per-LID hungry backpressure
threshold based on the number of free buffer pool segments (M) available, as
follows:
THRESHOLD_H = N * FREE_SEGEMENT_H, where the value of N is as
defined for FREE_SEGEMENT_S.
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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