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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 64/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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64
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
9.3.7 Block base 0x1000 registers
SPI-3 ingress packet length configuration register
(Block_base 0x1000 + Register_offset 0x00-0x3F)
TABLE 72 - SPI-3 INGRESS PACKET LENGTH
CONFIGURATION REGISTER
Field
Bits
MIN_LENGTH
7:0
Reserved
15:8
MAX_LENGTH
29:16
Reserved
30:31
There is one set of SPI-3 ingress packet length configuration registers per
SPI-3 ingress interface. Each SPI-3 ingress interface has 64 registers, one for
each of the allowed LIDs supported per SPI-3 interface. Each register has read
and write access. The mnimumand maximumpacket lengths per LID are
provisioned using the SPI-3 ingress packet length configuration register. The
bit fields of a SPI-3 ingress packet length configuration register are described.
Length
8
8
14
2
Initial Value
0x40
0x00
0x5EE
0x0
MIN_LENGTH
SPI-3 ingress mnimumpacket length. The mnimum
packet length is programmed from0 to 255 bytes. The resolution of the mnimum
packet length is one byte.
MAX_LENGTH
SPI-3 ingress maximumpacket length. The maximum
packet length is programmed from0 to 16,383 bytes. The resolution of the
maximumpacket length is one byte.
9.3.8 Block base 0x1100 registers
SPI-4 egress port descriptor table (Block_base
0x1100 + Register_offset 0x00-0x3F)
TABLE 73 - SPI-4 EGRESS PORT DESCRIPTOR
TABLE (64 ENTRIES)
Field
Bits
MAX_BURST_H
3:0
MAX_BURST_S
7:4
DIRECTION
9:8
Reserved
31:10
There are four sets of SPI-4 egress port descriptor tables, one per SPI-3
interface. The mnimumand maximumSPI-4 egress burst lengths per LID are
provisioned using a SPI-4 egress port descriptor table. Each SPI-4 egress port
descriptor table has read and write access. The bit fields of a SPI-4 egress port
descriptor table are described. These fields need to be programmed only for
SPI-4 egress (DIRECTION=0 in Table 74-SPI-4 egress direction code
assignment).
Length
4
4
2
22
Initial Value
0xF
0xF
0x3
0x000
MAX_BURST_H
device has declared hungry through the FIFO status channel. The number in
the MAX_BURST_H field is taken to mean that one more than that number
multiplied by 16 is the maximumhungry burst length. For example, programmng
the number 3 into the MAX_BURST_H field results in a maximumhungry burst
size of (3 + 1) x 16 = 64 bytes.
SPI-4 egress per-LID burst length when the attached
MAX_BURST_S
device has declared starving through the FIFO status channel. The number in
the MAX_BURST_S field is taken to mean that one more than that number
SPI-4 egress per-LID burst length when the attached
multiplied by 16 is the maximumstarving burst length. For example, program-
mng the number 7 into the MAX_BURST_S field results in a maximumstarving
burst size of (7 + 1) x 16 = 128 bytes. The MAX_BURST_S field should not be
set to less than the MAX_BURST_H field.
DIRECTION
cessor, directed to a SPI-3 egress port, to the SPI-4 egress port, or discarded.
The Path selection is defined for each of the 64 LIDs by the associated
DIRECTION field as shown in the following table
.
The SPI-4 egress traffic can be captured by the mcropro-
DIRECTION
00
01
10
11
Path
SPI-4
Associated SPI-3
Capture to mcroprocessor
Discard
TABLE 74 - SPI-4 EGRESS DIRECTION CODE
ASSIGNMENT
9.3.9 Block base 0x1200 registers
SPI-3 ingress port descriptor tables (Block_base
0x1200 + Register_offset 0x00-0x3F)
TABLE 75 - SPI-3 INGRESS PORT DESCRIPTOR
TABLE (BLOCK_BASE 0x1200 +
REGISTER_OFFSET 0X00-0X3F)
Field
Bits
M
8:0
Reserved
15:9
Reserved
20:16
Reserved
23:21
FREE_SEGMENT
28:24
Reserved
31:29
Length
9
7
5
3
5
3
Initial Value
0x000
0x00
0x00
0x0
0x00
0x0
There is one set of 64 SPI-3 ingress port descriptor tables per SPI-3 ingress
interface. The SPI-3 ingress port descriptor tables are at Block_base 0x1200
+ Register_offset 0x00-0x3F and have read and write access. Each SPI-3
ingress interface has 64 table entries for per-LID provisioning of Mand
FREE_SEGMENT fields. The SPI-3 ingress port descriptor tables are used to
control the amount of buffering and the free segment backpressure threshold
of the available buffer segment pool for a SPI-3 ingress on a per-LID basis.
Each SPI-3 buffer segment pool is 128 Kbytes, divided into 508 segments
of 256 bytes per segment. These 508 segments are shared among the LIDs
initially programmed into the NR_LID fields. A SPI-3 ingress LID can be allocated
the maximumnumber of segments out of the available buffer segments, or can
be programmed to fewer segments by decreasing the Mfield.
The FREE_SEGMENT field is used, along with the Mfield, to set the free
segment backpressure threshold for a LID on a SPI-3 ingress.
M
The number of 256-byte buffer pool segments on a SPI-3 ingress port
allocated to a LID. The range of Mis 0x000 to 0x1FC (508 base 10), but can
not exceed the number set by the choice of NR_LID [Block_base 0x1300 +
Register_offset 0x00].
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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