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参数资料
| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 60/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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60
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
There is one register for SPI-3 egress fill level register per SPI-3 interface.
Each register has read-only access. The bit fields of the SPI-3 egress fill level
register are described.
ADD_PAR_ERR
3 egress LP through the ADD_PAR_ERR bit field. The LP affected by the
ADD_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.
0=No parity error introduced
1=Introduce a single address parity error on a SPI-3 egress LP
A single address parity error is introduced on a SPI-
DAT_PAR_ERR
egress LP through the DAT_PAR_ERR bit field. The LP affected by the
DAT_PAR_ERR bit field is enumerated in the PORT_ADDRESS field.
0=No parity error introduced
1=Introduce a single data parity error on a SPI-3 egress LP
A single data parity error is introduced on a SPI-3
PORT_ADDRESS
the DAT_PAR_ERR bit fields is enumerated in the PORT_ADDRESS field. The
value of the PORT_ADDRESS is set from0x00 to 0xFF.
The LP affected by both the ADD_PAR_ERR and
SPI-3 egress fill level register (Block_base 0x0700
+ Register_offset 0x03)
TABLE 58 - SPI-3 EGRESS FILL LEVEL REGISTER
(REGISTER_OFFSET=0x03)
Field
Bits
FILL_CUR
3:0
Reserved
4
E_FCLK_AV
5
FILL_CUR
register, the value read fromit will change rapidly and is used for internal
diagnostics only.
Current SPI-3 egress buffer fill level. Since this is a real-time
I_FCLK_AV
Current SPI-3 egress clock availability is checked here.
0=SPI-3 egress clock transitions were not detected on a
SPI-3 port
1=SPI-3 egress clock transitions were detected on a SPI-
3 port
SPI-3 egress max fill level register (Block_base
0x0700 + Register_offset 0x04)
TABLE 59 - SPI-3 EGRESS MAX FILL LEVEL REGIS-
TER (REGISTER_OFFSET=0x04)
Field
Bits
FILL_MAX
3:0
Length
4
1
1
Initial Value
0x0
0x0
0b0
Length
4
Initial Value
0x0
There is one register for SPI-3 egress max fill Level per SPI-3 interface. Each
register has read-only access, and is cleared after reading. 0xF is the highest
filling level, meaning all egress buffers had been full at some time since the last
read of the FILL_MAX field. The units of FILL_MAX are one-sixteenth of the
available egress buffering. Each unit is equal to 128 bytes. The bit field of the
SPI-3 egress max fill Level register is described.
FILL_MAX
of the SPI-3 egress Max Fill Level Register
MaximumSPI-3 egress buffer fill level since the last read
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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