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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 65/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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65
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
An example of the use of the buffer segment pool follows. For a SPI-3 ingress
interface that will never have more than four LIDs, set the NR_LID field for this
interface to 0x01. This allows 256 buffer segments for a LID, with the total number
of buffer segments for all 4 LIDs equal to 508. Let’s say you want only 64 buffer
segments for one of the LIDs. Programfield Mfor that LID to 0x040 (64 base
10). Let’s say you want to backpressure the SPI-3 ingress interface when 48
of the 64 allocated buffers for this LID are full. In other words, you want to exert
SPI-3 ingress backpressure when only 16 segments remain for this LID. Since
M=0x040, N=4 fromthe description of the Mfield above [Block_base 0x1200].
Setting the FREE_SEGMENT field to 4 then yields the desired THRESHOLD
of 16.
TABLE 77 - NR_LID FIELD ENCODING
NR_LID
Maximum Number
of LIDs (base 10)
Maximum Buffer Segments
for a LID (base 10)
508
256
128
64
32
16
0b000
0b001
0b010
0b011
0b100
0b101
1
4
8
16
32
64
SPI-3 to SPI-4 flow control register (Block_base
0x1300 + Register_offset 0x01)
TABLE 78 - SPI-3 TO SPI-4 FLOW CONTROL REG-
ISTER (REGISTER_OFFSET 0x01)
Field
Bits
CREDIT_EN
0
BURST_EN
1
Reserved
7:2
A SPI-3 to SPI-4 flow control register has read and write access. There is
one SPI-3 to SPI-4 flow control register per SPI-3 ingress. The bit fields of the
SPI-3 to SPI-4 flow control register are described.
Length
1
1
6
Initial Value
0b1
0b0
0x00
CREDIT_EN
interpreted as status or credit information as selected by the CREDIT_EN flag
in the SPI-3 to SPI-4 flow control Register. If the status mode is used, data will
be egressed until the status is changed by the attached device. If the credit mode
is used, the SPI-4 egress will issue only one credit’s worth data burst and then
wait for another credit fromthe status channel before issuing another LID burst.
0=Status mode
1=Credit mode
The information received over the FIFO status channel is
BURST_EN
to an LP. This feature is included to relieve systems with long latency between
updates. When this feature is not enabled, only one burst per LP is allowed into
the SPI-4 egress buffers.
0=Disable burst enable
1=Enable burst enable
Multiple Burst Enable allows more than one burst to be sent
FREE_SEGMENT
The FREE_SEGMENT field is used to define the SPI-
3 ingress per-LID free segment backpressure threshold based on the number
of free buffer segments (M) available, as follows:
THRESHOLD = N * FREE_SEGEMENT,
Where the value of N is defined as a function of the domain of M:
M[8:0]
N (base 10)
16
8
4
2
1
0x100 to 0x1FC
0x080 to 0x0FF
0x040 to 0x07F
0x020 to 0x03F
0x000 to 0x01F
The THRESHOLD thus defined is the number of free segments available for
a LID at the time of backpressure initiation.
9.3.10 Block base 0x1300 registers
The SPI-3 ingress to SPI-4 egress Packet Fragment Processor and flow
control registers are at Block_Base 0x1300.
SPI-3 to SPI-4 PFP register (Block_base 0x1300 +
Register_offset 0x00)
TABLE 76 - SPI-3 TO SPI-4 PFP REGISTER
(REGISTER_OFFSET 0x00)
Field
NR_LID
Reserved
A SPI-3 ingress to SPI-4 egress PFP (Packet Fragment Processor) Register
has read and write access. There is one SPI-3 to SPI-4 PFP Register per SPI-
3 ingress. The bit fields of an 8-bit SPI-3 to SPI-4 PFP Register are described.
Bits
2:0
7:3
Length
3
5
Initial Value
0b011
0x0
NR_LID
The maximumnumber of LIDs per SPI-3 physical ingress
interface that will ever be used is programmed into the NR_LID field. Once
configured after reset, this value can not be changed. Fewer LIDs can be used
by not activating some of the LIDs, but more LIDs than the value in NR_LID are
not allowed and will generate an error. The NR_LID field is important, as the
buffer segment pool is divided among the number of LIDs programmed into the
NR_LID field.
A 128 Kbyte SPI-3 to SPI-4 buffer segment pool for storing data bursts for
the SPI-4 egress is available for each SPI-3 physical port. A configurable part
of this buffer segment pool can be assigned to each of the possible LIDs allowed
by the NR_LID field value per SPI-3 physical interface. The buffer size for a LID
can be configured in multiples (M) of 256 bytes. Modifications of the buffer size
allocated to a LID are supported only when the logical port associated to the LID
is disabled. Attempts to allocate more memory than available will generate an
allocation error event. The indirect access module will discard the attempt.
A 128 Kbyte SPI-3 to SPI-4 buffer segment pool is divided into 508 buffer
segments. Each buffer segment is equal to 256 bytes. The buffer segments are
shared among the number of logical ports defined by the static NR_LID
configuration. The buffer segments do not have to be equally shared among
the LIDs. One buffer segment corresponds to a data burst to be forwarded to
the SPI-4 egress interface.
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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