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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 43/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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43
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
8.2.5 SPI-4 status channel software
The SPI-4 status channel may be configured to either LVTTL or LVDS by
loading the appropriate status channel binary file to activate the firmware.
Download LVTTL.bin when using LVTTL status mode. Download LVDS.bin
when using LVDS status mode. This step should be performed as the third step
in the chip configuration sequence after reset in section 8.2.1.
The download process is described.
Direct write (0x20, 0x01); /*Write register 0x20 with 0x01 to reset */
Delay at least 5ms
Direct write (0x36, 0x07);
ind_write(0x00c8, 0xdcb0);
Open LVTTL.bin or LVDS.bin file
number = file length
addr = 0x0e00;
if ( number % 2 == 0 )
number /=2;
else
number = number/2 + 1;
for ( i = 0; i < number; i ++ )
{
scr_fp.Read(ch, 2);
data = (ch[1] << 8) |ch[0];
ind_write(addr, data);
addr ++;
addr ++;
}
close file
ind_write(0x00c6, 0x0e00);
ind_write(0x00c8, 0xc860);
Direct write (0x36, 0x00);
8.2.6 IDT88P8344 layout guidelines
SPI-3 LAYOUT GUIDELINES
1) Series termnate SPI-3 traces that are greater than 1/2 inch in end-to-
end length. Place the series resistor as close as possible to the driver, but no
more than 1/2 inch away fromthe driving end. SPI-3 inputs must have ringing
controlled to prevent the SPI-3 inputs fromgoing more than 0.5 Volts below
ground. Use the IBIS models for more accurate results with the specific devices
being used.
2) Mnimze all SPI-3 data and control trace lengths to not exceed the
T
D-MAX
- T
SETUP
requirement. For example, if the SPI-3 clock is 104 MHz, T
D-
of a device is 5.65 ns, and T
of the attached device is 1 ns, the maximum
PCB trace delay Table 18 permtted is 3 ns (Unit Interval - T
- T
). This
translates to a maximumPCB trace length for data and control lanes of 13.5
inches, if the loaded PCB trace delay is 220 picoseconds per inch. This is for
zero T
margin, and does not include any margin for clock driver skew.
Clock driver or clock trace skew could reduce the T
SETUP
margin in this example.
3) Match all SPI-3 clock lengths to within the T
D-MIN
- T
requirement. For
example, if T
for the device is 1.5 ns, and T
for the attached device
is 0.5 ns, the worst case PCB clock trace skew for zero T
margin (defined
in this example as the maximumPCB trace delay that the SPI-3 ingress clock
of the attached device can exceed the trace delay of the SPI-3 egress clock
of the device and still meet the T
requirement of the attached device with
zero margin, assumng the fastest device [T
] and the worst case T
for
the attached device and no trace delay on the data and control lanes) is 1.7
ns (Table 15 (T
- T
)), for a maximumPCB clock trace difference of
7.6 inches. Trace delay on the data and control lanes would improve the T
margin in this example. This example does not include any margin for SPI-3
clock buffer skew.
4) Ensure a few nanoseconds of clock delay between one SPI-3 clock net
and other SPI-3 clock nets of the same frequency to mnimze simultaneous
switching noise. The IDT88P8344 OCLK[3:0] outputs have skew between
each output already built in, and so are useful in lowering simultaneous
switching noise. A SPI-3 clock net is defined to be the SPI-3 egress clock for
a device and the SPI-3 ingress clock for the attached device.
5) Route all SPI-3 traces as 50 Ohmembedded stripline (inner layer
referencing ground planes). For example, 8 ml wide 1/2 oz copper traces
sandwiched between ground planes with 10 ml dielectric spacing between
ground planes and signal planes yields 52 Ohms single-ended, using FR-4
with a relative dielectric constant (
ε
or D
) of 4.2. If the edge to edge spacing
between adjacent SPI-3 series termnated signals is 20 mls in this example,
crosstalk between adjacent signals can be kept to 2%. Use a field solver for
more accurate results.
An example timng budget Table 15, Zero Margin SPI-3 Timng budget, and
example trace lengths to achieve timng margin Table 16, Margin check for SPI-
3 timng, are shown. These timng budget tables do not include clock driver
relative skew incurred if different drivers are used for a SPI-3 egress and its
attached SP-3 ingress. These tables are based on timng only and do not
include such effects as crosstalk and rise time degradation.
SPI-4 LAYOUT GUIDELINES
1) Match the P and N trace lengths within an LVDS differential signal pair to
within 100 mls or less.
2) Match the group of all differential data, control, and clock signal lengths to
within 1/2 unit interval (DDR), or less, of each other (1/4 clock period). For
SPI-3Clock
Tsetup
Thold Td, mnimum Td, maximum Unit Interval Maximumdata Maximumdata Maximum MaximumClock
trace delay
0.65 ns
2.33 ns
5.65 ns
9.6 ns
trace length
13.5 in
clock skew
trace length
1.7 ns
104 MHz
1 ns
3 ns
7.6 in
TABLE 15 - ZERO MARGIN SPI-3 TIMING BUDGET
SPI-3Clock
Tsetup
Thold Td, mnimum Td, maximum
Egress
clock trace
4 inches
Ingress
clock trace data trace
8 inches
Longest
Shortest
data trace
4 inches
Tsetup
margin
2.33 ns
Thold
margin
1.48 ns
104 MHz
1 ns
0.65 ns
2.33 ns
5.65 ns
6 inches
TABLE 16 - MARGIN CHECK FOR SPI-3 TIMING
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相关代理商/技术参数 |
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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