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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 73/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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73
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
updating of the FIFO status channel LPs to the attached device. If less than the
maximum256 LPs are needed on the SPI-4 interface, the calendar entries
should be used for scheduling more frequent status updated for higher-speed
LPs. The value of time-critical LPs must appear multiple times in the table. For
example, a multi-PHY SPI-4 could have OC-48 channels appear in the
calendar at four times the rate of OC-12 channels, since the higher data rate of
the OC-48 channels would benefit frommore frequent FIFO status channel
updates. The LP field values range from0x00 to 0xFF. The IDT88P8344 and
the attached devices must have identical calendars.
LP
The LP value programmed schedules a status channel update
according to the calendar sequence.
9.4.7 Common module block base 0x0600 registers
SPI-4 egress calendar_1 (Block_base 0x0600)
TABLE 103 - SPI-4 EGRESS CALENDAR_1
(256 LOCATIONS)
Field
Bits
LP
7:0
The SPI-4 egress calendar_1 is at Block_base 0x0600 and had read and
write access. When the SPI-4 egress calendar_1 is selected, calendar_1 is in
use. There are 256 entries in the SPI-4 egress calendar_1 to schedule the
updating of the FIFO status channel LPs to the attached device. If less than the
maximum256 LPs are needed on the SPI-4 interface, the calendar entries
should be used for scheduling more frequent status updated for higher-speed
LPs. The value of time-critical LPs must appear multiple times in the table. For
example, a multi-PHY SPI-4 could have OC-48 channels appear in the
calendar at four times the rate of OC-12 channels, since the higher data rate of
the OC-48 channels would benefit frommore frequent FIFO status channel
updates. The LP field values range from0x00 to 0xFF. The IDT88P8344 and
the attached devices must have identical calendars.
Length
8
Initial Value
0xFF
LP
The LP value programmed schedules a status channel update
according to the calendar sequence.
9.4.8 Common module block base 0x0700 registers
SPI-4 egress configuration register_0 (Block_base
0x0700 + Register_offset 0x00)
TABLE 104 – SPI-4 EGRESS CONFIGURATION
REGISTER_0 (REGISTER_OFFSET 0x00)
Field
Bits
Reserved
2:0
E_CLK_EDGE
3
E_DSC
4
E_INSYNC_THR
9:5
E_OUTSYNC_THR
13:10
E_CSW_EN
14
Reserved
15
E_LOW
16
NOSTAT
17
The SPI-4 egress configuration register_0 is at Block_base 0x0700 and has
read and write access.
The SPI-4 egress configuration register_0 is used to set the state of the SPI-
4 egress interface. The bit fields of the SPI-4 egress configuration register_0 are
described.
Length
3
1
1
5
4
1
1
1
1
Initial Value
0
0
0
0x1F
0xF
0
0
1
0
E_CLK_EDGE
the E_CLK_EDGE field.
0=SPI-4 egress clock uses the rising clock edge
1=SPI-4 egress clock uses the falling clock edge
The SPI-4 egress clock active clock edge is selected using
E_DSC
egress data lines.
The E_DSC bit enables or disables de-skewing of the SPI-4
0=Data de-skewing is disabled
1=Data de-skewing is enabled (recommended)
E_INSYNC_THR
old is controlled using the E_INSYNC_THR field. It is recommended to use the
initial value.
The SPI-4 egress DIP-2 in-synchronization thresh-
E_OUTSYNC_THR
threshold is controlled using the E_OUTSYNC_THR field. It is recommended
to use the initial value.
The SPI-4 egress DIP-2 out-of-synchronization
E_CSW_EN
the switching of the active calendars following the reception of the calendar
selection word on the status channel. It is recommended to use the initial value.
0=Egress calendar switch is disabled. Only SPI-4 egress calen-
dar_0 is used.
1=Egress calendar switch is enabled. Calendar_0 or calendar_1
will be used.
The ingress calendar switch enable bit is used to enable
E_LOW
range.
The E_LOW field selects the SPI-4 egress clock frequency
0=SPI-4 egress clock is greater than or equal to 200 MHz
1=SPI-4 egress clock is less than 200 MHz
NOSTAT
NOSTAT is set, the status channel is ignored. There is no DIP-2 error checking,
and no status channel updating. The received status is fixed to starving. The
data channel is put into the IN_SYNCH state.
0=Normal status channel operation
1=No status channel option is selected
The NOSTAT bit enables the no status channel option. Once
SPI-4 egress configuration register_1 (Block_base
0x0700 + Register_offset 0x01)
TABLE 105 - SPI-4 EGRESS CONFIGURATION
REGISTER_1 (REGISTER_OFFSET 0x01)
Field
Bits
DATA_MAX_T
23:0
ALPHA
31:24
Length
24
8
Initial Value
0
0
The SPI-4 egress configuration register_1 is at Block_base 0x0700 and has
read and write access.
The SPI-4 egress configuration register_1 is used to set the state of the SPI-
4 egress FIFO status path interface. The bit fields of the SPI-4 egress
configuration register_1 are described.
DATA_MAX_T
time interval between scheduling of training sequences on the egress data path
interface. The purpose of the data training interval is to allow the de-skewing
of plus or mnus one bit time on the egress data interface if needed. The time is
set for the DATA_MAX_T field multiplied by 128 cycles.
The SPI-4 egress DATA_MAX_T field is the maximum
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