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参数资料
| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 74/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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74
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
ALPHA
data training sequence that must be scheduled every DATA_MAX_T cycles.
The value for alpha used is actually one more than the ALPHA value
programmed into the ALPHA field.
The SPI-4 egress ALPHA field is the number of repetitions of the
SPI-4 egress status register (Block_base 0x0700 +
Register_offset 0x02)
TABLE 106 - SPI-4 EGRESS STATUS REGISTER
(REGISTER_OFFSET 0x02)
Field
Bits
E_SYNCH
0
E_DSK_OOR
1
SCLK_AV
2
SPI-4 egress status register
The SPI-4 egress status register is at Block_base 0x0700 and has read-only
access.
The SPI-4 egress status register is used to set the state of the SPI-4 egress
synchronization.
The bit fields of the SPI-4 egress status register are described.
E_CAL_M
times the calendar sequence is repeated before a DIP-2 parity and “1 1” framng
words are inserted. The actual calendar_Mvalue used is one more than the
value programmed into the E_CAL_Mfield.
The E_CAL_M value programmed defines the number of
E_CAL_LEN
The E_CAL_LEN value programmed defines the length of
the SPI-4 egress calendar. The actual length of the calendar is four times one
more than the value programmed into the E_CAL_LEN field. For example, if
the E_CAL_LEN field is programmed to 0x3F, the actual value used is 0x100.
The resulting calendar length must be at least as large as the number of active
SPI-4 egress LPs.
SPI-4 egress diagnostics register (Block_base
0x0700 + Register_offset 0x05)
TABLE 108 – SPI-4 EGRESS DIAGNOSTICS REGIS-
TER (REGISTER_OFFSET 0x05)
Field
Bits
Length
1
1
1
Initial Value
0
0
0
E_SYNCH
nization state of the SPI-4 egress data path.
0=SPI-4 egress data path is out of synchronization
1=SPI-4 egress data path is in synchronization
The SPI-4 egress E_SYNCH field describes the synchro-
E_DSK_OOR
skew state of the SPI-4 egress data path.
0=SPI-4 egress data path de-skew is within range
1=SPI-4 egress data path de-skew is out of range
The SPI-4 egress E_DSK_OOR field describes the de-
SCLK_AV
state of the SPI-4 egress status channel clock. This function is not available if
SCLK < 0.5 MCLK..
0=SPI-4 egress status channel clock is not available
1=SPI-4 egress status channel clock is available
The SPI-4 egress SCLK_AV field describes the availability
SPI-4 egress calendar configuration register
(Block_base 0x0700 + Register_offset 0x03 - 0x04)
TABLE 107 - SPI-4 EGRESS CALENDAR CONFIGU-
RATION REGISTER (REGISTER_OFFSET 0x03 -
0x04)
Field
Bits
Length
Initial Value
E_CAL_M
E_CAL_LEN
7:0
13:8
8
6
0
0x01
The SPI-4 egress calendar configuration registers are at Block_base
0x0300 and has read and write access. The Register_offset for calendar_0 is
0x03. The register offset for calendar_1 is 0x04.
The bit fields of the SPI-4 egress calendar configuration register are
described.
The IDT88P8344 calendar length can be programmed to any multiple of 4
using suitable values for the calendar entries, calendar length and calendar
M If the adjacent device is unable to configure its calendar to be a multiple of
4, conversion logic may be needed between the adjacent device SPI-4
status signals and the 88P8344 signals.
Length
Value
1
1
4
2
Initial
E_FORCE_TRAIN
E_ERR_INS
E_DIP_NUM
BIT_DELAY
The SPI-4 egress diagnostics register is addressed fromBlock_base 0x0700
+ Register_offset 0x05. The SPI-4 egress diagnostics register has read and
write access.
E_FORCE_TRAIN
The E_FORCE_TRAIN field is used to force continu-
ous training on the SPI-4 egress status interface.
0=Normal status channel operation
1=Force continuous training on the SPI-4 egress status interface
0
1
0
0
0
0
5:2
7:6
E_ERR_INS
The E_ERR_INS field is used to insert the number of DIP-
4 errors on the SPI-4 egress data interface that have been programmed into
the E_DIP_NUMfield. After the DIP-4 errors are inserted, the E_ERR_INS field
will clear itself.
0=Normal status channel operation
1= Insert DIP-4 errors on the SPI-4 egress data interface
E_DIP_NUM
The E_DIP_NUMfield is used to create DPI-4 errors on the
SPI-4 egress data interface. The number of errors generated is equal to the
value of the E_DIP_NUMfield.
BIT_DELAY
The BIT_DELAY field is used to delay SPI-4 egress data bit
line 0 by the number of bits programmed into the BIT_DELAY field. This may
be used for diagnostics.
SPI-4 egress DIP-2 error counter (Block_base
0x0700 + Register_offset 0x06)
TABLE 109 - SPI-4 EGRESS DIP-2 ERROR
COUNTER (REGISTER_OFFSET 0x06)
Field
Bits
DIP_2
15:0
The SPI-4 egress DIP-2 error counter is addressed fromBlock_base
0x0700 + Register_offset 0x06. The SPI-2 egress DIP-2 error counter has read
access, and automatically clears itself after a read. The SPI-4 egress DIP-2 error
counter is used in port diagnostics to verify the integrity of the SPI-4 egress status
channel.
Length
16
Initial Value
0
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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