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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 58/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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58
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
EVEN_PARITY
A SPI-3 interface is provisioned to generate and to check
for odd or even parity. The PARITY_EN bit must be set for this to become
effective. Odd parity is standard for SPI-3 interfaces.
0=Odd parity on this port
1=Even parity on this port
PARITY_EN
A SPI-3 interface is provisioned to enable or disable parity
generation and checking, according to the state of the EVEN_PARITY bit.
0=Disable parity on this SPI-3 port
1=Enable parity on this SPI-3 port
WATERMARK
watermark value. 0x10 is the highest watermark that can be set, meaning all
ingress buffers will be full before backpressure will be initiated on a SPI-3 ingress
interface. The WATERMARK field value of 0x08 is used to set the watermark
for a half-full ingress buffer before tripping backpressure. The units of WATER-
MARK are one-sixteenth of the available ingress buffering per unit. Each unit
is equal to 128 bytes. BACKPRESSURE_EN must be set [Register_offset 0x01]
for the watermark to become effective. The watermark field is usually set to 0x10,
and the FREE_SEGMENT field of Table 75, SPI-3 ingress port descriptor tables
(Block_base 0x1200) is used for per LID backpressure.
A SPI-3 interface can be set to a SPI-3 ingress port
SPI-3 ingress configuration register (Block_base
0x0200 + Register_offset 0x01)
TABLE 51 - SPI-3 INGRESS CONFIGURATION
REGISTER (REGISTER_OFFSET=0x01)
Field
Bits
BACKPRESSURE_EN
0
FIX_LP
1
Reserved
31:2
There is one register for SPI-3 ingress configuration per SPI-3 interface.
Each register has read and write access.
The bit fields for a SPI-3 ingress configuration register are described in the
following paragraphs.
BACKPRESSURE_EN
enabled or disabled. Disabling backpressure means that data comng into the
ingress may be lost if the SPI-3 interface ingress buffers overflow. The SPI-3
interface can run at full-rate, however, since there will be no backpressure.
Attached devices that do not respond properly to backpressure should be
interfaced by disabling backpressure.
Enabling backpressure will cause the I_ENB signal to be asserted when the
ingress buffer fill level is equal to the WATERMARK value [Register_offset 0x00],
or the free segment buffer threshold Table 75, SPI-3 ingress port descriptor table
(Block_base 0x1200) has been reached for any active LID.
0=Disable backpressure on this SPI-3 ingress.
1=Enable backpressure on this SPI-3 ingress interface.
A SPI-3 interface can have backpressure
FIX_LP
is useful when there is only one LP on an interface, such as with some single-
PHY devices.
0= Do not fix logical port address to 0x00, but use the actual
LP found in the packet fragments.
1= Fix logical port address to 0x00
A SPI-3 interface can fix the logical port address to 0x00. This
SPI-3 ingress fill level register (Block_base 0x0200
+ Register_offset 0x02)
Length
1
1
30
Initial Value
0b1
0b0
0x0000
There is one register for SPI-3 ingress fill level register per SPI-3 interface.
Each register has read-only access. The bit fields of a SPI-3 ingress fill level
register are described.
FILL_CUR
register, the value read fromit will change rapidly and is used for internal
diagnostics only.
Current SPI-3 ingress buffer fill level. Since this is a real-time
I_FCLK_AV
Current SPI-3 ingress clock availability is checked here.
0=SPI-3 ingress clock not detected on a SPI-3 port
1=SPI-3 ingress clock transitions detected on a SPI-3 port
SPI-3 ingress max fill register (Block_base 0x0200
+ Register_offset 0x03)
TABLE 53 - SPI-3 INGRESS MAX FILL LEVEL
REGISTER (REGISTER_OFFSET=0x03)
Field
Bits
FILL_MAX
4:0
There is one register for SPI-3 ingress max fill level register per SPI-3
interface. Each register has read-only access, and is cleared after reading.
0x10 is the highest filling level, meaning all ingress buffers had been full at some
time since the last read of the FILL_MAX field. The units of FILL_MAX are one-
sixteenth of the available ingress buffering. Each unit is equal to 128 bytes. The
bit field of a SPI-3 ingress max fill level register is described. The Table 53 - SPI-
3 ingress max fill level register (Register_offset=0x03) is for diagnostics only.
TABLE 52 - SPI-3 INGRESS FILL LEVEL REGISTER
(REGISTER_OFFSET=0x02)
Field
Bits
FILL_CUR
4:0
I_FCLK_AV
5
Length
5
1
Initial Value
0x00
0b1
Length
5
Initial Value
0x00
FILL_MAX
the SPI-3 ingress max fill level register.
MaximumSPI-3 ingress buffer fill level since the last read of
9.3.3 Block base 0x0500 registers
SPI-3 egress LID to LP map (Block_base 0x0500 +
Register_offset 0x00-0x3F)
TABLE 54 - SPI-3 EGRESS LID TO LP MAP
Field
Bits
LP
7:0
ENABLE
8
BIT_REVERSAL
9
There are 64 SPI-3 egress LID to LP maps per SPI-3 interface, one per
potential SPI-3 LID.
The SPI-3 egress LID to LP maps have read and write access. The SPI-
3 egress LID to LP maps are used to map SPI-3 egress logical identifiers to SPI-
3 logical port addresses that are in-band with the SPI-3 egress packet fragments.
Length
8
1
1
Initial Value
0x00
0b0
0b0
LP
The LP programmed is associated to the LID with the same number
as the register address.
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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