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| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 34/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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34
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
4.4 Microprocessor interface to SPI-3 datapath
capture/insert configurable parameters
Enable insertion / capture of data to the SPI-3 or SPI-4 data stream(which
is dependent on the egress control register). For each direction, the following
are to be used:
- Data for insertion or data captured
- Data available: set when data is available. Asserted by device for capture,
asserted by mcroprocessor for insertion.
- LID: Logical Identifier of capture / insertion channel
- Length: length of data for insertion or capture
- Flags: SOP, EOP, address parity error, data parity error, packet error
There are separate instantiations of mcroprocessor insert capture buffers for
SPI-3 and SPI-4.
Capture data fragment
Packets can be captured fromthe SPI-3-4 streamand directed towards the
mcroprocessor. The capture buffer can store only one 256 byte packet
fragment. When the buffer is full the DATA_AVAILABLE flag is set and a SPI-
3 capture event is generated. The event is directed towards the interrupt module.
Read packet data fragment
The mcroprocessor needs to read a buffer to capture a packet fragment. It
verifies the DATA_AVAILABLE flag in the SPI-3 capture control register.
Mcroprocessor reads the packet fragment and EOP, SOP, ERROR, LID and
LENGTH fields fromthe SPI-3 data capture buffer. Mcroprocessor hands over
control of the capture buffer when it clears the DATA_AVAILABLE flag in the SPI-
3 data capture control register (Table 31 - SPI-3 data capture control register).
4.4.1 SPI-3 to ingress microprocessor interface
datapath
The diagrambelow shows the datapath through the device fromthe SPI-3
interface to the mcroprocessor capture interface.
The following is a description of the path taken by a fragment of data through
the device.
Data enters on a SPI-3 interface in fragments. Fragments are of equal length
except the last fragment of a packet which may be shorter. The LP address is
in-band with the data. The fragment enters a SPI-3 ingress buffer. SPI-3 LP
address, error information, SOP, and EOP are stored with the fragment. The
LP address is mapped to a LID. The fragment is stored in LID allocated buffer
segments.
The Table 80, SPI-3 egress port descriptor table (64 entries) is consulted,
and the PFP decides to send this LID to the mcroprocessor capture port. Data
is moved to the capture buffer along with the LP address. LID, error information,
SOP, and EOP. The data available bit is set. Data and control information are
read fromthe relevant register space through the mcroprocessor interface.
Figure 23. SPI-3 ingress to microprocessor capture interface datapath
…
…
JTAG
uproc
Chip Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
SPI-4.2
Min: 80 MHz
Max: 400 MHz
I
I
SPI-3 /
LID map
SPI-4 /
LID map
Main
Memory
A
LID Counters Memory
6370 drw15
Figure 22 . Mcroprocessor data capture buffer
6370 drw28
flags
length
data[1]
data[2]
data[255]
lid
data[0]
SOP
EA
ED
PAR
EOP
not used
EA
ED
PAR
data parity error
address parity error
packet error
7
0
i
t
t+1
t+258
e
t
t+1
t+258
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| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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