- 您现在的位置：买卖IC网 > PDF目录377488 > IDT88P8344BHGI (INTEGRATED DEVICE TECHNOLOGY INC) SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 PDF资料下载
参数资料
| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 29/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页
29
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
SPI-3 ingress to SPI-4 egress flow control
For control information there are two separate cases to consider: The case
that the SPI-3 physical interface port is configured in Link mode, and the case
that the SPI-3 is configured in PHY mode. Note that since the SPI-3 physical
interfaces are configured separately, the device is able to deal with the case that
some of the LP fragments have been received on a Link layer device SPI-3
interface and some have been received on a PHY layer device SPI-3 interface.
For a device in Link mode the Link device can only control the flow of data
through the RENB signal. Two modes of operation are implemented and
configurable for flow control on this interface – either the data can be allowed
to flow freely into the device or the RENB signal will be asserted if a condition
arises that one of the LPs is unable to receive another fragment. The first of these
modes is considered to have no Link layer device flow control, and the second
has Link layer device flow control.
For the no Link flow control mode, any data sent to an LP unable to receive
another fragment will cause an LP overflow.
For a device in Link mode the Link has complete knowledge of the fill level
of the data buffers in each of the LPs in the PHY. This knowledge is attained either
through byte level polling or packet level polling.
Both in Link and PHY modes, the data is collected to buffer segments
associated with an LP. The SPI-4 PFP is updated with the number of free
segments available to the LP. The SPI-4 PFP determnes which LP to service
based on two factors: whether the LP contains enough data for a burst, and the
starving / hungry / satisfied state of the LP. For details on the mapping of LPs
to LIDs, refer to Table 101 - SPI-4 egress LID to LP Map Block_base 0x0400
= Register_offset 0x00 - 0xFF.
SPI-3 ingress flow control registers
The following are implemented per SPI-3 interface, and there are four
instantiations per device.
Backpressure enable
Link mode only
Enables the assertion of the I_ENB pin when at least one active LID can not
accept data
If not enabled, the I_ENB signal will never be asserted in Link mode, possibly
leading to fragments being discarded.
SPI-4 egress flow control configurable parameters
All parameters as listed in SPI-4 implementation agreement:
CALENDAR_LEN: 4 to 1,024 in increments of 4
CALENDAR_M: 1 to 256 in increments of 1
MaxBurst1 (MaxBurst_S): 16 to 256 in increments of 16
MaxBurst2 (MaxBurst_H): 16 to 256 in increments of 16
Alpha: 1 to 256 in increments of 1
DATA_MAX_T: 1 to 4,294,967,040 in increments of 1
FIFO_MAX_T: 1 to 16,777,215 in increments of 1
SPI-4 egress low control calendar and shadow calendar
256 entries
SPI-4 egress flow control multiple burst enable
Allows more than one burst to be sent to an LP. This feature was included
to increase throughput in systems with long latency between updates.
Figure 17. SPI-3 ingress to SPI-4 egress flow control path
…
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
STATUS
I
Chip Counters Memory
I
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw12a
DATA PATH
STATUS
STATUS
The diagrambelow shows the SPI-3 ingress to SPI-4 egress flow control Path
through the IDT88P8344 device.
相关PDF资料 |
PDF描述 |
|---|---|
| IDTAMB0480 | ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM MODULES |
| IDTCSP2510DPGI | 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| IDTCSP2510DPG | SENSOR OPTICAL SLOTTED 1.0MM |
| IDTCSP2510D | 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
| IDTCSPT857CNL | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
发布紧急采购，3分钟左右您将得到回复。