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参数资料
| 型号： | IDT88P8344BHGI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA820 |
| 封装： | GREEN, PLASTIC, BGA-820 |
| 文件页数： | 32/98页 |
| 文件大小： | 601K |
| 代理商： | IDT88P8344BHGI |
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32
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIAL TEMPERATURE RANGE
APRIL 10, 2006
SPI-4 ingress to SPI-3 egress flow control
The SPI-4 control information is transmtted to the adjacent device. The
adjacent device determnes which LP to service next according to the status
information it receives fromthe IDT88P8344. The SPI-4 ingress data arrive in
bursts that are of equal length except for the last burst of a packet which may
be shorter.
The SPI-4 burst data is transferred to the per LID allocated buffer segments.
The addition of the data may cause an update of the SPI-4 status information
(starving, hungry, satisfied), and may change the SPI-3 STPA, DTPA, or PTPA
signals when in PHY mode.
For the control information there are two separate cases to consider: the case
that the SPI-3 is configured to Link mode, and the case that the SPI-3 is configured
to PHY mode. Note that since the SPI-3 physical interfaces are configured
separately, the IDT88P8344 device is able to deal with the case that some of
the LP fragments are to be transmtted on a Link SPI-3 interface and some are
to be transmtted on a PHY SPI-3 interface
When in PHY mode, the data is sent according the availability of the data in
the buffer segment pool. In the Link mode an extra consideration is taken to
account – that of the fill level of the ingress FIFOs in the adjacent device.
Backpressure threshold
- Number of free segments allocated to trigger backpressure for the LP
The diagrambelow shows the SPI-4 to SPI-3 flow control path through the
IDT88P8344 device.
Figure 20. SPI-4 ingress to SPI-3 egress flow control
…
…
JTAG
uproc
LID Counters Memory
4 x SPI-3
8 bit / 32 bit
Min: 19.44MHz
Max: 133MHz
STATUS
I
Chip Counters Memory
I
SPI-3 /
LID map
Main
Memory
A
SPI-4.2
Min: 80 MHz
Max:400 MHz
SPI-4 /
LID map
6370 drw13a
STATUS
STATUS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT88P8344BHI | 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 类别:集成电路 (IC) >> 专用 IC 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBC | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBC8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
| IDT89H10T4BG2ZBBCG | 功能描述:IC PCI SW 10LANE 4PORT 324BGA RoHS:是 类别:集成电路 (IC) >> 专用 IC 系列:PRECISE™ 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- 类型:调帧器 应用:数据传输 安装类型:表面贴装 封装/外壳:400-BBGA 供应商设备封装:400-PBGA（27x27） 包装:散装 |
| IDT89H10T4BG2ZBBCG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PCI SW 10LANE 4PORT 324BGA |
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