参数资料
| 型号： | KIT13892VLEVBEJ |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 109/158页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC13892 |
| 标准包装： | 1 |
| 主要目的： | 电源管理和用户界面 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC13892 |
| 主要属性： | 10 位 ADC，4 输出降压转换器，12 LDO |
| 次要属性： | 与 i.MX51、i.MX37、i.MX35、i.MX27 一起使用 |
| 已供物品： | 板，线缆，文档 |
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FUNCTIONAL DEVICE OPERATION
ADC SUBSYSTEM
a first order filtering of the signal across R1. Due to the sampling of the A to D converter and the filtering applied, the longer the
software waits before retrieving the information from the CC, the higher the accuracy. The capacitor will be connected between
Figure 31. Coulomb Counter Block Diagram
The CC results are available in the 2's complement CCOUT[15:0] counter. This counter is preferably reflecting 1 Coulomb per
LSB. As a reminder, 1 Coulomb is the equivalent of 1 Ampere during 1 second, so a current of 20 mA during 1 hour is equivalent
to 72C. However, since the resolution of the A to D converter is much finer than 1C, the internal counts are first to be rescaled.
This can be done by setting the ONEC[14:0] bits. The CCOUT[15:0] counter is then increased by 1 with every ONEC[14:0] counts
of the A to D converter. For example, ONEC[14:0] = 000 1010 0011 1101 BIN = 2621 DEC yields 1C count per LSB of
CCOUT[15:0] with R1 = 20 mOhm.
The CC can be reset by setting the RSTCC bit. This will reset the digital blocks of the CC and will clear the CCOUT[15:0]
counter. The RSTCC bit gets automatically cleared at the end of the reset period which may take up to 40 μ s. The CC is started
by setting the STARTCC bit. The CC is disabled by setting this bit low again. This will not reset the CC settings nor its counters,
so when restarting the CC with STARTCC, the count will continue.
When the CC is running it can be calibrated. An analog and a digital offset calibration is available. The digital portion of the
CC is by default permanently corrected for offset and gain errors. This function can be disabled by setting the CCCALDB bit.
However, this is not advisable.
In order to calibrate the analog portion of the CC, the CCCALA bit is set. This will disconnect the inputs of the CC from the
sense resistor and will internally short them together. The CCOUT[15:0] counter will accumulate the analog error over time. The
calibration period can be freely chosen by the implementer and depends on the accuracy required. By setting the ONEC[14:0] = 1
DEC this process is sped up significantly. By reading out the contents of the CCOUT[15:0] and taking into account the calibration
period, software can now calculate the error and account for it. Once the calibration period has finished the CCCALA bit should
be cleared again.
One optional feature is to apply a dithering to the A to D converter to avoid any error in the measurement due to repetitive
events. To enable dithering the CCDITHER bit should be set. In order for this feature to be operational, the digital calibration
should remain enabled, so the CCCALDB bit should not be set.
Table 98. Coulomb Counter Characteristics
Parameter
Sense resistor R1
Sensed current
On consumption
Resolution
Condition
Placed in Battery path of
Charger system
Through R1
CC active
1LSB Increment
Min
-–
± 1.0
–
–
Typ
20
–
10
381.47
Max
–
± 3000
20
–
Unit
m Ω
mA
μ A
μ C
MC13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
109
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