参数资料
| 型号： | KIT13892VLEVBEJ |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 98/158页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC13892 |
| 标准包装： | 1 |
| 主要目的： | 电源管理和用户界面 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC13892 |
| 主要属性： | 10 位 ADC，4 输出降压转换器，12 LDO |
| 次要属性： | 与 i.MX51、i.MX37、i.MX35、i.MX27 一起使用 |
| 已供物品： | 板，线缆，文档 |
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FUNCTIONAL DEVICE OPERATION
BATTERY INTERFACE AND CONTROL
FACTORY MODE
In factory mode, power is provided to the application with no battery present. It is not a situation which should occur in the field.
The factory mode is differentiated from a USB Host by, in addition to a valid VBUS, a UID being pulled high to the VBUS level
during the attach, see Connectivity .
In case of a serial path (M3 present), the application will be powered up with M1M2 fully on. The M3 is opened (non conducting)
to a separate BP from BATT. However, the internal trickle charge current source is not enabled. All the charger timers as well as
the power limiter are disabled.
In case of a single path (M3 replaced by a short, BATTFET floating), the behavior is similar to a normal charging case. The
application will power up and the charge current is set to the 500 mA minimum level. All the internal timers and pre-charger timers
are enabled, while only the charger timer and power limiter function are disabled.
In both cases, by setting the CHGAUTOVIB bit, the charge voltage and currents can be programmed. When setting the
CHGAUTOB bit the factory mode is exited.
USB LOW-POWER BOOT
USB low-power boot allows the application to boot with a dead battery within the 100 mA USB budget until the processor has
negotiated for the full current capability. This mode expedites the charging of the dead battery and allows the software to bring
up the LCD display screen with the message “Charging battery”. This is enabled on the IC by hardwiring the MODE pin on the
Table 79. MODE Pin Programming
MODE Pin State
Ground
VCOREDIG
Mode
Normal Operation
Low-power Boot Allowed
Below are the steps required for USB low-power booting:
1. First step: detect a potential low-power boot condition, and qualify if it is enabled.
a) VBUS present and not in Factory Mode (either via a wall charger or USB host, since the IC has no knowledge of what
kind of device is connected)
b) BP<BPON (full power boot if BP>BPON)
c) Board level enabling of LPB with MODE pin hardwired to VCOREDIG
d) M3 included in charger system (Serial path charging, not Single). If all of these are true, then LPBS=1 and the system
will proceed with LPB sequence. If any are false, LPBS = 0.
2. If LPBS = 0, then a normal booting of the system will take place as follows:
a) MODE = GND. The INT pin should behave normally, i.e. can go high during Watchdog phase based on any unmasked
interrupt. If BP>BATTON, the application will turn on. If BP < BATTON, the PMIC will default to trickle charge mode and
a turn on event will occur when the battery is charged above the BATTON threshold. The processor does not support a
low-power boot mode, so it powers up normally.
b) MODE = VCOREDIG. When coming from Cold Start the INT is kept low throughout the watchdog phase. The
processor detects this and will boot normally. The INT behavior is becomes 'normal' when entering On mode, and also
when entering watchdog phase from warm start.
3. If LPBS = 1, then the system will boot in low-power as follows:
a) Cold Start is initiated in a “current starved bring-up” limited by the charger system's DAC step ICHRG[3:0] = 0001 to
stay within 100 mA USB budget. The startup sequence and defaults as defined in the startup table will be followed.
Since VBUS is present the USB supplies will be enabled. The charge LED driver is maintained off.
b) After the power up sequence, but before entering Watchdog phase, thus releasing the reset lines, the charger DAC
current is stepped up to ICHRG[3:0] = 0100. This is in advance of negotiation and the application has to ensure that
the total loading stays below the un-negotiated 100 mA limit.
c) The INT pin is made high before entering watchdog phase and releasing RESETBMCU. All other interrupts are held off
during the watchdog phase. The processor detects this and starts up in a Low-power mode at low clock speed.
d) The application processor will enable the PHY in serial FS mode for enumeration.
e) If the enumeration fails to get the stepped up current, the processor will bring WDI low. The power tree is shut down,
and the charging system will revert to trickle recovery, LPBS reset to 0. (or any subsequent failure: WDI = 0). Also if
RESETB transitions to 0 while in LPB (i.e., if BP loading misbehaves and causes a UVDET for example), the system
will transition to USB trickle recover, LPBS reset to 0.
MC13892
Analog Integrated Circuit Device Data
98
Freescale Semiconductor
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