参数资料
| 型号： | KIT13892VLEVBEJ |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 40/158页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC13892 |
| 标准包装： | 1 |
| 主要目的： | 电源管理和用户界面 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC13892 |
| 主要属性： | 10 位 ADC，4 输出降压转换器，12 LDO |
| 次要属性： | 与 i.MX51、i.MX37、i.MX35、i.MX27 一起使用 |
| 已供物品： | 板，线缆，文档 |
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FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
INTERFACING OVERVIEW AND CONFIGURATION OPTIONS
The MC13892 contains a number of programmable registers for control and communication. The majority of registers are
accessed through a SPI interface in a typical application. The same register set may alternatively be accessed with an I 2 C
interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I 2 C interfaces. Further
details for each interface mode follow in this chapter.
Table 7. SPI / I 2 C Bus Configuration
Pin Name
SPI Mode Functionality
I2C Mode Functionality
CS
Configuration
, Chip Select
Configuration (44)
CLK
MISO
MOSI
SPI Clock
Master In, Slave Out (data output)
Master Out, Slave In (data input)
SCL: I 2 C bus clock
SDA: Bi-directional serial data line
A0 Address Selection (45)
Notes
43. CS held low at Cold Start configures interface for SPI mode; once activated, CS functions as the SPI Chip Select.
44.
45.
CS tied to VCORE at Cold Start configures interface for I 2 C mode; the pin is not used in I 2 C mode other than for configuration.
In I 2 C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses.
SPI INTERFACE
The MC13892 contains a SPI interface port, which allows access by a processor to the register set. Via these registers, the
resources of the IC can be controlled. The registers also provide status information about how the IC is operating, as well as
information on external signals.
The SPI interface pins can be reconfigured for reuse as an I 2 C interface. As a result, a configuration protocol mandates that
the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin. With the CS pin held low
during startup (as would be the case if connected to the CS driver of an unpowered processor, due to the integrated pull-down),
the bus configuration will be latched for SPI mode.
The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The
addressable register map spans 64 registers of 24 data bits each.
The general structure of the register set is given in the following table. Bit names, positions, and basic descriptions are
provided in SPI Bitmap . Expanded bit descriptions are included in the following functional chapters for application guidance. For
brevity's sake, references are occasionally made herein to the register set as the “SPI map” or “SPI bits”, but note that bit access
is also possible through the I 2 C interface option, so such references are implied as generically applicable to the register set
accessible by either interface.
Table 8. Register Set
Register
Register
Register
Register
0
1
2
3
4
5
6
7
8
9
10
11
Interrupt Status 0
Interrupt Mask 0
Interrupt Sense 0
Interrupt Status 1
Interrupt Mask 1
Interrupt Sense 1
Power Up Mode Sense
Identification
Unused
ACC 0
ACC 1
Unused
16
17
18
19
20
21
22
23
24
25
26
27
Unused
Unused
Memory A
Memory B
RTC Time
RTC Alarm
RTC Day
RTC Day Alarm
Switchers 0
Switchers 1
Switchers 2
Switchers 3
32
33
34
35
36
37
38
39
40
41
42
43
Regulator Mode 0
Regulator Mode 1
Power Miscellaneous
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
ADC 0
48
49
50
51
52
53
54
55
56
57
58
59
Charger 0
USB0
Charger USB1
LED Control 0
LED Control 1
LED Control 2
LED Control 3
Unused
Unused
Trim 0
Trim 1
Test 0
MC13892
Analog Integrated Circuit Device Data
40
Freescale Semiconductor
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