参数资料
| 型号： | KIT13892VLEVBEJ |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 85/158页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR MC13892 |
| 标准包装： | 1 |
| 主要目的： | 电源管理和用户界面 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC13892 |
| 主要属性： | 10 位 ADC，4 输出降压转换器，12 LDO |
| 次要属性： | 与 i.MX51、i.MX37、i.MX35、i.MX27 一起使用 |
| 已供物品： | 板，线缆，文档 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页当前第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页
FUNCTIONAL DEVICE OPERATION
SUPPLIES
product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VxEN bit while at the same time
an interrupt SCPI will be generated to flag the fault to the system processor.
The SCPI interrupt is maskable through the SCPM mask bit.
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, then not only is no interrupt generated, but also
the regulators will not automatically be disabled upon a short-circuit detection. However, the built-in current limiter will continue
to limit the output current of the regulator. Note that by default, the REGSCPEN bit is not set, so at startup none of the regulators
that are in an overload condition will be disabled
VAUDIO AND VVIDEO SUPPLIES
The primary applications of these power supplies are for audio, and TV-DAC. However these supplies could also be used for
other peripherals if one of these functions is not required. Low-power modes and programmable Standby options can be used
to optimize power efficiency during Deep Sleep modes.
An external PNP is utilized for VVIDEO to avoid excess on-chip power dissipation at high loads, and large differential between
BP and output settings. For stability reasons a small minimum ESR may be required. In the Low-power mode for VVIDEO an
internal bypass path is used instead of the external PNP. External PNP devices are always to be connected to the BP line in the
application. The recommended PNP device is the ON Semiconductor NSS12100XV6T1G which is capable of handling up to
250 mW of continuous dissipation at minimum footprint and 75 °C of ambient. For use cases where up to 500mW of dissipation
is required, the recommended PNP device is the ON Semiconductor ? NSS12100UW3TCG. For stability reasons a small
minimum ESR may be required.
VAUDIO is implemented with an integrated PMOS pass FET and has a dedicated input supply pin VINAUDIO.
The following tables contain the specifications for the VVIDEO, VAUDIO.
Table 54. VVIDEO and VAUDIO Voltage Control
Parameter
VVIDEO
VAUDIO
Value
00
01
10
11
00
01
10
11
Function
Output = 2.700 V
Output = 2.775 V
Output = 2.500 V
Output = 2.600 V
Output = 2.300 V
Output = 2.500 V
Output = 2.775 V
Output = 3.000 V
ILoad max
250 mA / 350 mA
250 mA / 350 mA
250 mA / 350 mA
250 mA / 350 mA
150 mA
150 mA
150 mA
150 mA
LOW VOLTAGE SUPPLIES
VDIG and VPLL are provided for isolated biasing of the Baseband system PLLs for clock generation in support of protocol and
peripheral needs. Depending on the lineup and power requirements, these supplies may be considered for sharing with other
loads, but noise injection must be avoided and filtering added if necessary, to ensure suitable PLL performance. The VDIG and
VPLL regulators have a dedicated input supply pin: VINDIG for the VDIG regulator, and VINPLL for the VPLL regulator. VINDIG
and VINPLL can be connected to either BP or a 1.8V switched mode power supply rail, such as from SW4 for the two lower set
points of each regulator VPLL[1:0] and VDIG[1:0] = [00], [01]. In addition, when the two upper set points are used VPLL[1:0] and
VDIG[1:0] = [10], [11], the inputs (VINDIG and VINPLL) can be connected to either BP of a 2.2 V nominal external switched mode
power supply rail to improve power dissipation.
Table 55. VPLL and VDIG Voltage Control
Parameter
VPLL[1:0]
VDIG[1:0]
Value
00
01
10
11
00
01
10
11
Function
output = 1.2 V
output = 1.25 V
output = 1.5 V
output = 1.8 V
output = 1.05 V
output = 1.25 V
output = 1.65 V
output = 1.8 V
ILoad max
50 mA
50 mA
50 mA
50 mA
50 mA
50 mA
50 mA
50 mA
Input Supply
BP or 1.8 V
BP or 1.8 V
BP or External Switcher
BP or External Switcher
BP or 1.8 V
BP or 1.8 V
BP or External Switcher
BP or External Switcher
MC13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
85
相关PDF资料 |
PDF描述 |
|---|---|
| KIT17C724EPEVBE | KIT FOR 17C7242CH HBRIDGE PWR IC |
| KIT33810EKEVME | BOARD EVAL FOR MC33810 |
| KIT33811EGEVBE | KIT EVAL 33811 SOLENOID MON IC |
| KIT33812ECUEVME | KIT DESIGN FOR 33812/S12P |
| KIT33812EKEVBE | BOARD EVALUATION FOR MC33812 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| KIT-1395 | 制造商:Anderson Power Products (APP) 功能描述:KIT |
| Kit-1395G1 | 制造商:ANDERSON POWER PRODUCTS 功能描述:KIT |
| Kit-1395G10 | 制造商:ANDERSON POWER PRODUCTS 功能描述:KIT |
| Kit-1395G2 | 制造商:ANDERSON POWER PRODUCTS 功能描述:KIT |
| Kit-1395G3 | 制造商:ANDERSON POWER PRODUCTS 功能描述:KIT |
发布紧急采购，3分钟左右您将得到回复。