118
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
Interrupt Request Register 1
CPU Mode Register
Address 00FB16
Address 00FC16
b7 b6 b5 b4 b3 b2 b1 b0
B
After reset RW
CPU Mode Register
0, 1
2
3, 4
0
1
Name
Functions
Processor mode bits
(CM0, CM1)
0 0: Single-chip mode
0 1:
1 0:
Not available
1 1:
Fix these bits to “1.”
1
Stack page selection
bit (CM2) (See note)
1
b1 b0
0: 0 page
1: 1 page
10
0
5
6
Main Clock (X IN–XOUT)
stop bit
(CM6)
CPU mode register (CPUM) (CM) [Address FB 16]
RW
XCOUT drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
0: Oscillating
1: Stopped
7
Internal system clock
selection bit
(CM7)
RW
0: XIN–XOUT selected
(high-speed mode)
1: XCIN–XCOUT selected
(high-speed mode)
Note: This bit is set to “1” after the reset release.
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1 (IREQ1) [Address 00FC
B
Name
Functions
After reset RW
Interrupt Request Register 1
0
0 : No interrupt request issued
1 : Interrupt request issued
Timer 1 interrupt
request bit
(TM1R)
1
Timer 2 interrupt
request bit
(TM2R)
2
Timer 3 interrupt
request bit
(TM3R)
3
Timer 4 interrupt
request bit
(TM4R)
4
OSD interrupt request
bit
(CRTR)
5VSYNC interrupt
request bit
(VSCR)
6
A-D conversion INT3
interrupt request bit (ADR)
7
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
0
V
0
V
0
V
0
V
0
V
0
V
0
V
V: “0” can be set by software, but “1” cannot be set.
—
16
]
R
Nothing is assigned. This bit is a write disable bit.
When this bit is read out, the value is “0.”
1
0