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参数资料
| 型号： | M37274MA-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP52 |
| 封装： | 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-52 |
| 文件页数： | 64/131页 |
| 文件大小： | 2049K |
| 代理商： | M37274MA-XXXSP |
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38
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
4 ! set value of the start bit position
register ! reference clock period
<
Fig. 31. Caption Position Register
(6) Reference Voltage Generating Circuit and
Comparator
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
Reference voltage generating circuit
This circuit generates a reference voltage (slice voltage) by using
the amplitude of the clock run-in pulse in line specified by the data
slice line specification circuit. Connect a capacitor between the
VHOLD pin and the VSS pin, and make the length of wiring as short
as possible so that a leakage current may not be generated.
Comparator
The comparator compares the voltage of the composite video signal
with the voltage (reference voltage) generated in the reference
voltage generating circuit, and converts the composite video signal
into a digital value.
(7) Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit. For start bit detection, it is possible to select one
of the following two types by using bit 1 of clock run-in register 2
(address 00E716).
After the lapse of the time corresponding to the set value of the
start bit position register (address 00E116), the first rising of the
composite video signal is detected as a start bit.
The time is set in bits 0 to 6 of the start bit position register (address
00E116) (refer to Figure 32). Set a value fit for the following
conditions.
Figure 32 shows the structure of the start bit position register.
Time from the falling of the horizontal
synchronizing signal to the last rising
of the clock run-in
Fig. 32. Start Bit Position Register
Caption position register
(CP : address 00E016)
Specification main data slice line
70
100
Fix these bits to “1002”
70
Start bit generating time
Time from a falling of the
horizontal synchronizing signal
to occurrence of a start bit = 4
! set value (“0016” to “7F16”) !
reference clock period
Start bit position register
(SP : address 00E116)
DSC1 bit 7 control bit
0 : Generation of 16 pulses
1 : Generation of 16 pulses and
detection of clock run-in
pulse (4 to 6 pulses)
Time from the faling of the horizontal
synchronous signal to occurrence of
the start bit
<
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