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参数资料
| 型号： | M37274MA-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP52 |
| 封装： | 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-52 |
| 文件页数： | 33/131页 |
| 文件大小： | 2049K |
| 代理商： | M37274MA-XXXSP |
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128
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
Vertical Position Register 2i
Window L Register 2
Address 021F16
Addresses 023016 to 023B16
Vertical Position Register 1i
Addresses 022016 to 022B16
b7 b6 b5 b4 b3 b2 b1 b0
Window L register 2 (WL2) [Address 021F 16]
B
Name
Functions
After reset
R W
Window L Register 2
0, 1 Control bits of window
top boundary
(WL20 to WL27)
(See note 1)
Top boundary position (high-order 2 bits)
TH !
(setting value of low-order 2 bits of WL2 ! 162
+ setting value of high-order 4 bits of WL1 ! 161
+ setting value of low-order 4 bits of WL1 ! 160)
Indeterminate RW
Notes 1: Set values fit for the following condition: (WH1+WH2)<(WL1+WL2)
2: TH is cycle of HSYNC.
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are indeterminate.
2
to
7
Indeterminate R—
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 1i (VP1i) (i = 1 to 12) [Addresses 0220 16 to 022B16]
B
Name
Functions
After reset
R W
Vertical Position Register 1i
0
to
7
Control bits of vertical
display start positions
(VP1i0 to VP1i7)
(See note 1)
Vertical display start positions
(low-order 8 bits)
TH !
(setting value of low-order 2 bits of VP2i ! 162
+ setting value of low-order 4 bits of VP1i ! 161
+ setting value of low-order 4 bits of VP1i ! 160)
Indeterminate RW
Notes 1: Set values except “00 16” “0116” to VP1i when VP2i is “00 16.”
2: TH is cycle of HSYNC.
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 2i (VP2i) (i = 1 to 12) [Addresses 0230 16 to 023B16]
B
Name
Functions
After reset
R W
Vertical Position Register 2i
0, 1 Control bits of vertical
display start positions
(VP1i0 to VP1i7)
(See note 1)
Vertical display start positions
(high-order 2 bits)
TH !
(setting value of low-order 2 bits of VP2i ! 162
+ setting value of low-order 4 bits of VP1i ! 161
+ setting value of low-order 4 bits of VP1i ! 160)
Indeterminate RW
Nothing is assigned. These bits are write disable bits.
When these bits are read out, the values are indeterminate.
2
to
7
Indeterminate R—
Notes 1: Set values except “00 16” “0116” to VP1i when VP2i is “00 16.”
2: TH is cycle of HSYNC.
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