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42
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
Fig. 40. Sync Pulse Counter Register
(12) Synchronous Signal Counter
The synchronous signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronous signal Vsep as a count source.
The count value in a certain time (T time) generated by f(XIN)/213 or
f(XIN)/213 is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
The latch value can be obtained by reading out the sync pulse counter
register (address 020F16). A count source is selected by bit 5 of the
sync pulse counter register.
The synchronous signal counter is used when bit 0 of PWM mode
register 1 (address 02EA16).
Figure 40 shows the structure of the sync pulse counter and Figure
41 shows the synchronous signal counter block diagram.
Fig. 41. Synchronous Signal Counter Block Diagram
Sync pulse counter register
(SYC : address 020F16)
Count value
Count source
Count time
0: HSYNC
signal
1: Composite
sync signal
f(XIN)/213
(1024 s, f(XIN) = 8 MHz)
70
Reset
5-bit counter
Latch (5 bits)
f(XIN)/213
Composite
sync signal
HSYNC signal
Counter
Sync pulse
counter register
Data bus
Selection gate : connected to black
colored side when
reset.
b5