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参数资料
| 型号： | M37274MA-XXXSP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP52 |
| 封装： | 0.600 INCH, 1.778 MM PITCH, SHRINK, PLASTIC, DIP-52 |
| 文件页数： | 86/131页 |
| 文件大小： | 2049K |
| 代理商： | M37274MA-XXXSP |
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58
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
The display position in the vertical direction is determined by count-
ing the horizontal sync signal (HSYNC). At this time, when VSYNC and
HSYNC are positive polarity (negative polarity), it starts to count the
rising edge (falling edge) of HSYNC signal from after fixed cycle of
rising edge (falling edge) of VSYNC signal. So interval from rising edge
(falling edge) of VSYNC signal to rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) for avoiding
jitter. The polarity of HSYNC and VSYNC signals can select with the
I/O polarity control register (address 021716).
Fig. 60. Supplement Explanation for Display Position
The vertical position for each block can be set in 1024 steps (where
each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in
vertical position register 1i (i = 1 to 12) (addresses 022016 to 022B16)
and values “0016” to “0316” in vertical position register 2i (i = 1 to 12)
(addresses 023016 to 023B16). The structure of the vertical position
registers is shown in Figure 61.
Fig. 61. Vertical Position Registers
The horizontal position is common to all blocks, and can be set in
256 steps (where 1 step is 4TOSC, TOSC being the oscillating cycle
for display) as values “0016” to “FF16” in bits 0 to 7 of the horizontal
position register (address 00CF16). The structure of the horizontal
position register is shown in Figure 62.
Fig. 62. Horizontal Position Register
When bits 0 and 1 of the I/O polarity control register
(address 021716) are set to “1” (negative polarity)
VSYNC signal input
VSYNC control
signal in
microcomputer
0.25 to 0.50 [
s]
( at f(XIN) = 8MHz)
Period of counting
HSYNC signal
(Note 2)
HSYNC
signal input
Not count
12345
Notes 1 : The vertical position is determined by counting falling edge of
HSYNC signal after rising edge of VSYNC control signal in the
microcomputer.
2 : Do not generate falling edge of H SYNC signal near rising edge
of VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles
or more.
8 machine cycles
or more
8 machine cycles
or more
7
Vertical position register 1i
(i = 1 to 12)
(VP1i : addresses 022016 to 022B16)
Control bits of vertical display
start positions (Note)
Vertical display start positions (low-order 8 bits)
TH ! (setting value of low-order 2 bits of VP2i ! 16
+ setting value of low-order 4 bits of VP1i ! 16
+ setting value of low-order 4 bits of VP1i ! 16 )
Note : Set values except “00 16” and “0116” to VP1i when VP2i is “00 16.”
2
1
0
7
Vertical position register 2i
(i = 1 to 12)
(VP2i : addresses 023016 to 023B16)
Control bits of vertical display
start positions (Note)
Vertical display start positions (high-order 2 bits)
TH
(setting value of low-order 2 bits of VP2i ! 16
setting value of low-order 4 bits of VP1i ! 16
setting value of low-order 4 bits of VP1i ! 16 )
2
1
0
Note : The setting value synchronizes with the V SYNC.
7
Horizontal position register
(HP : address 00CF16)
Control bits of horizontal display
start positions
Horizontal display start positions
4TOSC ! (setting value of high-order 4 bits ! 16
+setting value of low-order 4 bits ! 16 )
1
0
!
+
0
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