![](http://datasheet.mmic.net.cn/120000/M37274MA-XXXSP_datasheet_3558749/M37274MA-XXXSP_23.png)
23
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
subject
to change.
MITSUBISHI MICROCOMPUTERS
SERIAL I/O
The M37274MA-XXXSP has a built-in serial I/O which can either trans-
mit or receive 8-bit data serially in the clock synchronous mode.
The serial I/O block diagram is shown in Figure 14. The synchronous
clock I/O pin (SCLK), and data output pin (SOUT) also function as port
P4, data input pin (SIN) also functions as port P1.
Bit 2 of the serial I/O mode register (address 021316) selects whether
the synchronous clock is supplied internally or externally (from the
P46/SCLK pin). When an internal clock is selected, bits 1 and 0 select
whether f(XIN) or f(XCIN) is divided by 8, 16, 32, or 64. To use SOUT
and P46/SCLK pins for serial I/O, set the corresponding bits of the
port P4 direction register (address 00C916) to “0.” To use SIN pin for
serial I/O, set the corresponding bit of the port P1 direction register
(address 00C316) to “0.”
Fig. 14. Serial I/O Block Diagram
The operation of the serial I/O is described below. The operation of
the serial I/O differs depending on the clock source; external clock or
internal clock.
8
Serial I/O shift register (8)
Data bus
Serial I/O
interrupt request
Selection gate: Connect to
black side at
reset.
Synchronous
circuit
Frequency divider
1/8
1/4
1/16
SM1
SM0
Serial I/O counter (8)
SM5 : LSB
MSB
S
SM2
1/2
XIN
SIN
SOUT
SCLK
1/2
(Address 021416)
XCIN
1/2
CM7
1/2
Note : When the data is set in the serial I/O register (address 0214 16), the register functions as the serial I/O shift register.
(Note)
CM : CPU mode register
SM : Serial I/O mode register