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参数资料
| 型号： | MT18HTF12872G-40EC2 |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 1/36页 |
| 文件大小： | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
09005aef80e5e626
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
1
2003 Micron Technology, Inc.
512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
DDR2 REGISTERED
SDRAM DIMM
MT18HTF6472 – 512MB
MT18HTF12872 – 1GB (ADVANCE)
MT18HTF25672 – 2GB (ADVANCE)
For the latest data sheet, please refer to the Micron Web
Features
240-pin, dual in-line memory module (DIMM)
Fast data transfer rates: PC2-3200 or PC2-4300
Utilizes 400 MT/s and 533 MT/s DDR2 SDRAM
components
ECC, 1-bit error detection and correction
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
512MB (64 Meg x 72), 1GB (128 Meg x 72)
2GB (256 Meg x 72)
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
VDDSPD = +1.7V to +3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Differential clock inputs (CK, CK#)
Commands entered on each rising CK edge
DQS edge-aligned with data for READs
DQS center-aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four or eight internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3 and 4
Posted CAS# additive latency (AL): 0, 1, 2, 3, and 4
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
READ burst interrupt supported by another READ
WRITE burst interrupt supported by another WRITE
Adjustable data-output drive strength
Concurrent auto precharge option is supported
Auto Refresh (CBR) and Self Refresh Mode
Figure 1: 240-Pin DIMM (MO-237 R/C “C”)
7.8125s maximum average periodic refresh
interval
64ms, 8,192-cycle refresh
Off-chip driver (OCD) impedance calibration
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
NOTE:
1. Consult factory for availability of lead-free prod-
ucts.
2. CL = CAS (READ) Latency; Registered mode will
add one clock cycle to CL.
OPTIONS
MARKING
Package
240-pin DIMM (standard)
G
240-pin DIMM (lead-free)1
Y
Frequency/CAS Latency2
3.75ns @ CL = 4 (DDR2-533)
-53E
5.0ns @ CL = 3 (DDR2-400)
-40E
Table 1:
Address Table
512MB
1GB
2GB
Refresh Count
8K
Row Addressing
8K (A0–A12)
16K (A0–A13)
Device Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1, BA2)
Device Configuration
256Mb (64 Meg x 4)
512Mb (128 Meg x 4)
1Gb (256 Meg x 4)
Column Addressing
2K (A0–A9, A11)
Module Rank Addressing
1 (S0#)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2DY-667F1B5 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE CUSTOM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
| MT18HTF12872M3Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
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