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参数资料
| 型号： | MT18HTF12872G-40EC2 |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 21/36页 |
| 文件大小： | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
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512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
28
2003 Micron Technology. Inc.
NOTE:
1. Timing and switching specifications for the register listed above are critical for proper operation of the DDR2
SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the
module. Detailed information for this register is available in JEDEC Standard JESD82.
2. This parameter is not necessarily production tested.
3. Data inputs must be low a minimum time of tact (MAX), after RESET# is taken HIGH.
4. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact (MAX), after RESET# is
taken LOW.
Table 19:
Register Timing Requirements and Switching Characteristics
SYMBOL
PARAMETER
CONDITION
0°C
TOPR +55°C
VDD = +1.8V ±0.1V
UNITS
MIN
MAX
VOH
IOH = -TBD mA
TBD
–
V
VOL
IOL = TBD mA
–
TBD
V
II
All Inputs
VI = VDD or GND
–
5
A
IDD
Static Standby
RESET# = GND
–
100
A
Static Operating
RESET# = VDD, VI = VIH(AC) or VIL(AC), I0 = 0
–
TBD
mA
IDDD
Dynamic Operating – Clock Only
RESET# = VDD, VI = VIH(AC) or VIL(AC), I0 =
0; CK and CK# switching 50% duty cycle
TBD
A
Dynamic Operating – per each
data input, 1:1 mode
RESET# = VDD, VI = VIH(AC) or VIL(AC), I0 = 0;
CK and CK# switching 50% duty cycle; one
data input switching at tCK/2, 50% duty
cycle
TBD
Dynamic Operating – per each
data input, 1:2 mode
RESET# = VDD, VI = VIH(AC) or VIL(AC), I0 = 0;
CK and CK# switching 50% duty cycle; one
data input switching at tCK/2, 50% duty
cycle
TBD
CI
Data Inputs
VI = VREF ±250mV
2.5
3.5
pF
CK and CK#
VICR = 0.9V, VID = 600mV
2
3
RESET
VI = VDD or GND
TBD
Table 20:
Register Electrical Characteristics
Note: 1
REGISTER
SYMBOL
PARAMETER
CONDITION
0°C
TOPR +55°C
VDD = +1.8V ±0.1V
UNITS
NOTES
MIN
MAX
SSTL
(bit pattern
by JESD82)
fclock
Clock Frequency
–
270
MHz
tw
Pulse Duration
1
–
ns
tact
Differential Inputs
Active Time
–TBD
ns
tinact
Differential Inputs
Inactive Time
–TB
ns
tsu
Setup Time
Data Before CK HIGH, CK# LOW
0.7
–
ns
Data Before CK HIGH, CK# LOW
0.5
–
ns
ODT, CKE, and Data before CK
HIGH, CK# LOW
0.5
–
th
Hold Time
OKE, CKE, and Data after CK
HIGH, CK# LOW
0.50
–
ns
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| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
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