参数资料
型号: MT18HTF12872G-40EC2
元件分类: DRAM
英文描述: 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240
封装: DIMM-240
文件页数: 15/36页
文件大小: 672K
代理商: MT18HTF12872G-40EC2
512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
22
2003 Micron Technology. Inc.
Table 16:
DDR2 IDD Specifications and Conditions – 2GB
Notes: 1–5; notes appear on page 26; values shown for DDR2 SDRAM components only
PARAMETER/CONDITION
SYMBOL
-53E -40E
UNITS
Operating one bank active-precharge current;
tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD0TBD
TBD
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS
MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1TBD
TBD
mA
Precharge power-down current;
All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING.
IDD2P
TBD
mA
Precharge quiet standby current;
All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
IDD2Q
TBD
mA
Precharge standby current;
All device banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD2N
TBD
mA
Active power-down current;
All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING.
Fast PDN Exit
MR[12] = 0
IDD3P
TBD
mA
Slow PDN Exit
MR[12] = 1
IDD3P
TBD
mA
Active standby current;
All device banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP = tRP(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING.
IDD3N
TBD
mA
Operating burst write current;
All device banks open, Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W
TBD
mA
Operating burst read current;
All device banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD4R
TBD
mA
Burst refresh current;
tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
IDD5TBD
TBD
mA
Self refresh current;
CK and CK# at 0V; CKE
0.2V; Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING.
IDD6TBD
TBD
mA
Operating bank interleave read current;
All device banks interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD)-1
x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is
HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during
DESELECTs; Data bus inputs are SWITCHING; See IDD7 Conditions for detail.
IDD7TBD
TBD
mA
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