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参数资料
| 型号： | MT18HTF12872G-40EC2 |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 36/36页 |
| 文件大小： | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
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512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
9
2003 Micron Technology. Inc.
Figure 4: DDR2 Power-Up and Initialization
NOTE:
1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up.
One of the following two conditions (a or b) MUST be met:
a) VDD, VDDL, and VDDQ are driven from a single power converter output.
VTT may be 0.95V maximum during power up.
VREF tracks VDDQ/2.
b) Apply VDD before or at the same time as VDDL.
Apply VDDL before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
2. Either a NOP or DESELECT command may be applied.
3. 200 cycles of clock (CK, CK#) are required before a READ command can be issued.
4. Two or more REFRESH commands are required.
5. EMR OCD Default command is required unless OCD adjust mode is used by the system; either command must be fol-
lowed by an EMR OCD Exit command.
6. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command, ACT = ACTIVE command, RA =
Row Address, BA = Device Bank Address.
7. DQS represents DQS, DQS#. DQ represents DQ0–DQ3.
8. CKE pin uses LVCMOS input levels prior to state T0. After state T0, CKE pin uses SSTL_18 input levels.
9. The LM command for EMR(2) and EMR(3) may be before or after LM command for MR (Tf0) and EMR (Te0). ADDRESS
represents A0–A12, BA0, and BA1(512MB, 1GB), or A0–A12, BA0, BA1, and BA2 (2GB). A10 should be HIGH at states Tb0
and Tg0 to ensure a PRECHARGE (all device banks) command is issued.
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tVTD1
CKE
Rtt
Power-up:
VDD and stable
clock (CK, CK#)
T = 200s (min)
High-Z
DM7
DQS7
High-Z
ADDRESS9
CK
CK#
tCL
VTT1
VREF
VDDL
VDDQ
COMMAND6
NOP2
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PRE
T0
Ta0
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DON’T CARE
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tCL
tCK
VDD
ODT
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DQ7
High-Z
T = 400ns (min)
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Tb0
200 cycles of CK3
EMR with
DLL Enable
MR with
DLL Reset
tMRD
tRP
tRFC
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CODE9
LM
PRE
LM
REF4
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REF4
LM5
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CODE9
Tg0
Th0
Ti0
Tj0
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MR w/o
DLL Reset
tMRD
EMR with
OCD Default5
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LM5
LM
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Tk0
Tl0
Tm0
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tMRD
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tMRD
CODE9
EMR with
OCD Exit5
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CODE9
Te0
Tf0
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VALID3
VALID
NORMAL
OPERATION
EMR(2)9
EMR(3)9
tMRD
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LM9
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CODE9
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tRP
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Tc0
Td0
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LVCMOS
LOW LEVEL8
SSTL_18
LOW LEVEL8
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相关PDF资料 |
PDF描述 |
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| MT18HVF6472PY-53EXX | 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2DY-667F1B5 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE CUSTOM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
| MT18HTF12872M3Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
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