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参数资料
| 型号： | MT18HTF12872G-40EC2 |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 34/36页 |
| 文件大小： | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
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512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
7
2003 Micron Technology. Inc.
General Description
The
MT18HTF6472,
MT18HTF12872,
and
MT18HTF25672 DDR2 SDRAM modules are high-
speed, CMOS, dynamic random-access 512MB, 1GB,
and 2GB memory modules organized in x72 (ECC)
configuration. DDR2 SDRAM modules use internally
configured quad-bank (512MB, 1GB) or eight-bank
(2GB) DDR2 SDRAM devices.
DDR2 SDRAM modules use double data rate archi-
tecture to achieve high-speed operation. The double
data rate architecture is essentially a 4n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for the DDR2 SDRAM module
effectively consists of a single 4n-bit-wide, one-clock-
cycle data transfer at the internal DRAM core and four
corresponding n-bit-wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS, DQS#) is transmit-
ted externally, along with data, for use in data capture
at the receiver. DQS is a strobe transmitted by the
DDR2 SDRAM device during READs and by the mem-
ory controller during WRITEs. DQS is edge-aligned
with data for READs and center-aligned with data for
WRITEs.
DDR2 SDRAM modules operate from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to DDR2 SDRAM modules
are burst-oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed. The address bits registered coincident with
the READ or WRITE command are used to select the
device bank and the starting column location for the
burst access.
DDR2 SDRAM modules provide for programmable
read or write burst lengths of four or eight locations.
DDR2 SDRAM supports interrupting a burst read of
eight with another read, or a burst write of eight with
another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst access.
The pipelined, multibank architecture of DDR2
SDRAMs allows for concurrent operation, thereby pro-
viding high, effective bandwidth by hiding row pre-
charge and activation time.
A self refresh mode is provided, along with a power-
saving power-down mode.
All inputs are compatible with the JEDEC standard
for SSTL_18. All full drive-strength outputs are
SSTL_18-compatible.
PLL and Register Operation
DDR2 SDRAM modules operate in registered mode,
where the command/address input signals are latched
in the registers on the rising clock edge and sent to the
DDR2 SDRAM devices on the following rising clock
edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL) on the module receives and
redrives the differential clock signals (CK, CK#) to the
DDR2 SDRAM devices. The registers and PLL mini-
mize system and clock loading. Registered mode will
add one clock cycle to CL.
Serial Presence-Detect Operation
DDR2 SDRAM modules incorporate serial pres-
ence-detect (SPD). The SPD function is implemented
using a 2,048-bit EEPROM. This nonvolatile storage
device contains 256 bytes. The first 128 bytes can be
programmed by Micron to identify the module type
and various SDRAM organizations and timing parame-
ters. The remaining 128 bytes of storage are available
for use by the customer. System READ/WRITE opera-
tions between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Functional Description
The DDR2 SDRAM module uses a double data rate
architecture to achieve high-speed operation. The
DDR2 architecture is essentially a 4n-prefetch archi-
tecture, with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR2 SDRAM module consists of a
single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and four corresponding n-bit-
wide, one-half-clock-cycle data transfers at the I/O
pins.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2DY-667F1B5 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE CUSTOM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
| MT18HTF12872M3Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
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