- 您现在的位置：买卖IC网 > PDF目录299522 > MT18HTF12872G-40EC2 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 PDF资料下载
参数资料
| 型号： | MT18HTF12872G-40EC2 |
| 元件分类： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM MODULE, 0.6 ns, DMA240 |
| 封装： | DIMM-240 |
| 文件页数： | 17/36页 |
| 文件大小： | 672K |
| 代理商： | MT18HTF12872G-40EC2 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
512MB, 1GB, 2GB (x72, REGISTERED)
PC2-3200, PC2-4300, 240-Pin DDR2 SDRAM DIMM
09005aef80e5e626
Micron Technology, Inc., reserves the right to change products or specifications without notice.
HTF18C64_128_256x72G_A.fm - Rev. A 9/03 EN
24
2003 Micron Technology. Inc.
Data
S
tr
obe
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS output access time from CK/CK#
tDQSCK
-450
+450
-500
+500
ps
DQS falling edge to CK rising – setup time
tDSS
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
300
350
ps
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
00
ps
DQS write preamble
tWPRE
0.25
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching
transition
tDQSS
WL - 0.25 WL + 0.25 WL - 0.25 WL + 0.25
tCK
Comma
nd
and
Addr
es
s
Address and control input pulse width for
each input
tIPW
0.6
tCK
Address and control input setup time
tIS
250
350
ps
Address and control input hold time
tIH
375
475
ps
CAS# to CAS# command delay
tCCD
22
tCK
ACTIVE to ACTIVE (same bank) command
tRC
60
65
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
ACTIVE to PRECHARGE command
tRAS
45
70,000
45
70,000
ns
Internal READ to precharge command
delay
tRTP
7.5
ns
Write recovery time
tWR
15
ns
Auto precharge write recovery + precharge
time
tDAL
tWR + tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
10
ns
PRECHARGE command period
tRP
15
20
ns
LOAD MODE command cycle time
tMRD
22
tCK
OCD Drive mode delay
tOIT
0120
12
ns
CKE low to CK,CK# uncertainty
tDELAY
4.375
5.83
ns
Re
fr
e
s
h REFRESH to REFRESH command interval
tRFC
75
70,000
75
70,000
ns
Average periodic refresh interval
tREFI
7.8
s
Table 18:
AC Operating Conditions (Continued)
Notes: 1–5; notes appear on page 26; 0°C
TOPR +55°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC CHARACTERISTICS
-53E
-40E
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS NOTES
相关PDF资料 |
PDF描述 |
|---|---|
| MT18HVF6472PY-53EXX | 64M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| MT28C128532W30DFW-F706P85BBWT | SPECIALTY MEMORY CIRCUIT, PBGA77 |
| MT28C128564W30DBW-F706P85KBTWT | SPECIALTY MEMORY CIRCUIT, PBGA77 |
| MT28C128532W30EFW-F705-P856KBBWT | SPECIALTY MEMORY CIRCUIT, PBGA77 |
| MT28C128532W18EFW-F605-P706BTWT | SPECIALTY MEMORY CIRCUIT, PBGA77 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MT18HTF12872JDY-667F1D4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL PBF DIMM 1.8V FULLY - Bulk |
| MT18HTF12872M2DY-667F1B4 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE PBF DIMM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2DY-667F1B5 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE CUSTOM 1.8V FULLY BUFFERED - Trays |
| MT18HTF12872M2Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
| MT18HTF12872M3Y-53EF1 | 制造商:Micron Technology Inc 功能描述:1GB 128MX72 DDR2 SDRAM MODULE COMMERCIAL CUSTOM 1.8V REGISTE - Bulk |
发布紧急采购，3分钟左右您将得到回复。